United Microelectronics Corp.

Ming-Yen Liu

Ke-Feng Lin

Wen-Chung Chang

Min-Hsuan Tsai

Cherng-En Sun

Tseng Hsun Liu

Wen-Fang Lee

Yu-Hsien Lin

Chiu-Te Lee

Nien-Chung Li

Shih-Teng Huang

Ching-Nan Hwang

Ya-Huang Huang

Yu-Kang Shen

A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substrate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

Method for fabricating transistor structure

A transistor structure includes a substrate, having a gate region and a first trench in the substate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

Transistor structure and method for fabricating the same

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a doped region in the substrate; forming a thermal oxide layer on the substrate and the doped region; removing the thermal oxide layer to form a first recess; forming an epitaxial layer on the substrate and in the first recess; and forming a gate dielectric layer in the epitaxial layer.

Semiconductor device and method for fabricating the same

A multi-time programmable (MTP) memory includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer. The inter-gate dielectric layer is disposed on the floating gate, and a thickness of the inter-gate dielectric layer at edges of the floating gate is larger than a thickness of the inter-gate dielectric layer in a central portion of the floating gate. The control gate is disposed on the inter-gate dielectric layer.

Multi-time programmable memory

Growing community of inventors

Hsinchu, Taiwan

Ming-Yen Liu