Taiwan Semiconductor Manufacturing Comp. Ltd.

E Ink Holdings Inc.

Ming-Yen Chuang

Katherine H Chiang

Yun-Feng Kao

Chung-Te Lin

Chien-Hao Huang

Neil Quinn Murray

Wenchin Lin

Chia-En Huang

Ping-Wei Wang

Shih-Hao Lin

Mauricio Manfrini

Chih-Chuan Yang

Chia-Chun Yeh

Hsin-Wen Su

Jui-Lin Chen

Chenchen Jacob Wang

Hsiao-Wen Zan

Chuang-Chuang Tsai

Gao-Ming Wu

Chang-Lin Yang

Pei-Chen Yu

Chia Yu Ling

A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.

Vertical transistors and methods for forming the same

Some embodiments relate to a memory device. The memory device includes a transistor having a first source/drain (S/D) region and a second S/D region, a first S/D contact disposed over the first S/D region, the first S/D contact extending lengthwise in a first direction, a second S/D contact disposed over the second S/D region, a first via landing on the first S/D contact, the first via extending lengthwise in a second direction different from the first direction, a second via landing on the second S/D contact, the first via having a length measured in the second direction that is larger than the second via, a first conductive line coupled to the first via, a second conductive line coupled to the second via, and a memory structure disposed above the transistor and coupled to the second conductive line.

Memory device and method of forming the same

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a memory cell stack over a substrate. The memory cell stack comprises a tunnel barrier layer, a free layer over the tunnel barrier layer, a capping dielectric layer over the free layer, and a conductive capping layer on the capping dielectric layer. A conductive shunting structure is formed along outer sidewalls of the free layer, outer sidewalls of the capping dielectric layer, and outer sidewalls of the conductive capping layer. A bottommost point of the conductive shunting structure in contact with the free layer is disposed above a bottom surface of the free layer.

MRAM structure with high TMR and high PMA

A semiconductor structure includes a two-dimensional array of unit cell structures overlying a substrate. Each unit cell structure includes an active layer, a gate dielectric underlying the active layer, two gate electrodes underlying the gate dielectric, and two source electrodes and a drain electrode overlying the active layer. Word lines underlie the active layers. Each unit cell structure includes portions of a respective set of four word lines, which includes two word lines that are electrically connected to two electrodes in the unit cell structure and two additional word lines that are electrically isolated from the two electrodes in the unit cell structure.

Access transistors in a dual gate line configuration and methods for forming the same

A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.

Vertical access transistors and methods for forming the same

A disclosed capacitor structure includes a support structure including a plurality of elongated structures each extending along a longitudinal direction, a transverse direction, and a vertical direction. The plurality of elongated structures includes an alternating stack of first dielectric layers and second dielectric layers, a bottom electrode formed over the support structure, a third dielectric layer formed over the bottom electrode, and a top electrode formed over the third dielectric layer. Each of the first dielectric layers includes a first width along the transverse direction and each of the second dielectric layers includes a second width along the transverse direction. In various embodiments, the first width may be less than the second width such that each of the plurality of elongated structures include walls including a corrugated width profile as a function of distance along the vertical direction. The capacitor structure may be formed in a BEOL process.

Capacitor structure and method of making the same

A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.

Transistor device having ultraviolet attenuating capability

An integrated circuit includes an array of word lines, and an array of memory cells configured to receive selection signals from the array of word lines. Each memory cell in the array of memory cells is connected to one or more data lines in a set of data lines. The integrated circuit also includes a read-write driver which is connected to the set of data lines and is configured to receive a flip-refresh control signal. The read-write driver has a catch circuit configured to store a first bit value related to a stored bit value in a selected memory cell. The read-write driver is configured to store into the selected memory cell a second bit value which is a bit inversion of the stored bit value.

Method of and apparatus for refreshing memory devices

A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 10cm. A semiconductor structure and a manufacturing method are also provided.

Transistor, semiconductor structure, and manufacturing method thereof

A semiconductor device includes a substrate and a transistor structure disposed on the substrate. The transistor structure includes a channel region and a source/drain electrode disposed on the channel region. The channel region includes a lower channel portion and a plurality of upper channel portions protruding from the lower channel portion into the source/drain electrode to form an uneven interface between the channel region and the source/drain electrode.

Transistor structure having improved electrode conductance and method for manufacturing the same

A semiconductor die includes semiconductor substrate and interconnection structure. Interconnection structure includes first conductive lines, first conductive patterns, first pillar stacks, second pillar stacks, gate patterns. First conductive lines extend parallel to each other in first direction and are embedded in interlayer dielectric layer. First conductive patterns are disposed in row along first direction and are embedded in interlayer dielectric layer beside first conductive lines. First pillar stacks include first pairs of metallic blocks separated by first dielectric material blocks. Second pillar stacks include second pairs of metallic blocks separated by second dielectric material blocks. Each second pillar stack is electrically connected to respective first conductive pattern. Gate patterns extend substantially perpendicular to first conductive lines. Each gate pattern directly contacts one respective second pillar stack and extends over a group of first pillar stacks.

Semiconductor device and manufacturing method thereof

Dual gate vertical thin film transistors and methods for forming the same

A memory integrated circuit is provided. The memory integrated circuit includes a first memory array, a second memory array and a driving circuit. The first and second memory arrays are laterally spaced apart, and respectively include: memory cells, each including an access transistor and a storage capacitor coupled to the access transistor; bit lines, respectively coupled to a row of the memory cells; and word lines, respectively coupled to a column of the memory cells. The driving circuit is disposed below the first and second memory arrays, and includes sense amplifiers. Each of the bit lines in the first memory array and one of the bit lines in the second memory array are routed to input lines of one of the sense amplifiers.

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Hsinchu, Taiwan

Ming-Yen Chuang