Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Yang Huang

Bao-Ru Young

Tung-Heng Hsieh

Yung Feng Chang

An IC includes a first standard cell (SC) having a first circuit area (CA) and a first transition area (TA) placed on an edge of the CA; and a SChaving a CAand a TAplaced on an edge of CA'. CAincludes a first and a second active region (ARand AR) longitudinally oriented along a first direction (D), and a first gate stack (G) along a D⊥Dand extending over ARand AR. Gincludes a first gate segment (GS) contacting ARand a GScontacting AR. GSand GSare different in composition. GSand GSare associated with a pFET and a nFET, respectively. TAincludes a Glongitudinally oriented along Dand spans between opposite cell edges of the SC. Gis a lengthwise uniform gate stack. SCis placed in abutment with the SCsuch that TAand TAshare a common edge.

Integrated standard cell structure

Semiconductor structures and methods are provided. A method according to the present disclosure includes providing a workpiece that includes a plurality of active regions including channel regions and source/drain regions, and a plurality of dummy gate stacks intersecting the plurality of active regions at the channel regions, the plurality of dummy gate stacks including a device portion and a terminal end portion. The method further includes depositing a gate spacer layer over the workpiece, anisotropically etching the workpiece to recess the source/drain regions and to form a gate spacer from the gate spacer layer, forming a patterned photoresist layer over the workpiece to expose the device portion and the recessed source/drain regions while the terminal end portion is covered, and after the forming of the patterned photoresist layer, epitaxially forming source/drain features over the recessed source/drain regions.

Growing community of inventors

Hsinchu, Taiwan

Ming-Yang Huang