Boe Technology Group Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Dolby Laboratories Licensing Corporation

Huawei Technologies Co., Limited

Telefonaktiebolaget Lm Ericsson (publ)

International Business Machines Corporation

Chengdu Boe Optoelectronics Technology Co., Ltd.

Lenovo (beijing) Limited

Samsung Electronics Co., Ltd.

Apple Inc.

Fujitsu Corporation

Dell Products Inc.

Vmware, Inc.

Marvell International Limited

Chinese Academy of Sciences

Ming Wang

Dongfang Wang

Qinghe Wang

Guangyao Li

Lie Lu

Haitao Wang

Tongshang Su

Alan Jeffrey Seefeldt

Liangchen Yan

Yang Zhang

Ning Liu

Liugang Zhou

Jun Feng Liu

Haitao Liu

Wei Li

Ke Dai

Bin Zhou

Jun Cheng

Liang Wang

Jing Yan Ma

Xiaoxia Cai

Yingbin Hu

Guangcai Yuan

Yi Qu

Leilei Cheng

Qing Ql Li

Giulio Cengarle

Ce Zhao

Xiaofeng Yin

Zhihui Zhang

Yongchao Huang

Li Long Chen

Tao Li

Ming Hsi Wang

Yue Wang

Shuo Li

Jun Zhang

Lei Huang

Yue He

Wei Song

Jie Liu

Regunathan Radhakrishnan

ShengYan Sun

Rhonda J Wilson

Xu Wu

Rui Peng

Yu Zhang

Yongqian Li

Yi Zhang

Lixiang Xu

Jian Zhang

Wei Sun

Jun Zhu

Meng Li

Xuehuan Feng

Can Yuan

Zhidong Yuan

Liang Zhang

Zheng Liu

Qian Zhang

Dirk Jeroen Breebaart

Nicolas R Tsingos

Zhen Wang

Sheng Yan Sun

David S McGrath

Fei Wang

Xiaodong Xu

Wenjie Peng

Zhibin Yu

Yang Li

Xiaoqiang Li

Kai Xu

Yu Ma

Peng Chen

Lei Du

Xuejing Sun

Tong Li

Lei Gao

Xiaodong Wang

Hiroyuki Hayashi

Jing Chen

Tianyi Cheng

Yulong Shi

Liang Sun

Dan Liu

Bo Feng

Wenbin Jia

Tobias Scholand

Lin Zhang

Song Yang

Jun Tian

Xu Liang Li

Zhiwei Shuang

Rong Liu

Yue Yang

Peng Sun

Jin Wang

Xinxin Wang

Feng Guo

Yanfeng Li

The present disclosure relates to radar signal processing, and a harmonic radar based on a field programmable gate array (FPGA) and deep learning. Specifically, a signal processing module generates a baseband linear frequency modulation (LFM) signal, converts the baseband LFM signal into an analog signal, and mixes the analog signal with a local carrier frequency signal to obtain a radio frequency (RF) transmitting signal. A second-harmonic signal/a third-harmonic signal is generated after the RF transmitting signal irradiates a target, and is transmitted to a second-harmonic receiver/a third-harmonic receiver correspondingly; after undergoing low-noise amplification and filtering by the corresponding harmonic receiver, the second-harmonic signal/the third-harmonic signal and a corresponding local oscillator signal are demodulated to obtain an echo baseband signal; and the echo baseband signal is amplified and sent to a signal processing module for processing after being quantified and converted by an analog-to-digital converter (ADC).

Harmonic radar based on field programmable gate array (FPGA) and deep learning

A system of predicting sensitivity ofagainst meropenem includes comprises a computer readable storage medium on which is stored a computer program. An Exp (−k) power value calculation method is implemented when the computer program is executed by a processor. The Exp(−k) power value calculation method comprises-includes following computing steps: S1: k value is calculated according to formula I, S2: Exp(−k) power value with natural constant e as base and −k as exponent is calculated.

System of predicting sensitivity ofagainst MeropeneM and method

A communication method and an apparatus. The method includes: receiving at least one piece of quality of service QoS information from a second terminal; determining first QoS information based on the at least one piece of QoS information; and determining a first bearer configuration based on the first QoS information, and forwarding data from the second terminal to a third terminal based on the first bearer configuration; or sending the first QoS information to a network device, receiving a first bearer configuration of the network device, and forwarding data from the second terminal to a third terminal based on the first bearer configuration.

Communication method and apparatus for improving transmission of QOS information in communication between terminals

A zearalenone functionalized graphene surface molecularly imprinted material, a preparation method therefor and the use thereof, which belong to the technical field of molecularly imprinted materials. The zearalenone functionalized graphene surface molecularly imprinted material is prepared by using RGO as a carrier, CDHB as a template molecule, 1-ALPP as a functional monomer, TRIM as a cross-linking agent, AIBN as an initiator, and acetonitrile as a pore-forming agent.

Zearalenone functionalized graphene surface molecularly imprinted material, preparation method therefor and use thereof

An array substrate, a display device and a fabrication method are provided. The array substrate includes a first metal layer at one side of a base substrate, the first metal layer including a light shielding part, a source, a drain in a display area; a second metal layer at a side, facing away from an active layer, of gate insulating layer, the second metal layer includes a gate, a source-landing electrode a drain-landing electrode in the display area, the source-landing electrode is in contact with the active layer and the source through a first via hole penetrating through the gate insulating layer and a buffer layer and exposing one end of the active layer, the drain-landing electrode is in contact with the active layer and the drain through a second via hole penetrating through the gate insulating layer and the buffer layer and exposing other end of the active layer.

Array substrate and display device

Provided is a method for manufacturing a display panel. The method includes: forming a first electrostatic protective circuit and a source and drain conductive pattern on a base substrate, the base substrate including a target cutting region, wherein the target cutting region is overlapped with an orthographic projection of the first electrostatic protective circuit on the base substrate, and the target cutting region is overlapped with an orthographic projection of the source and drain conductive pattern on the base substrate; removing the source and drain conductive pattern within the target cutting region; forming a to-be-cut display panel by forming a superstructure on the base substrate; and cutting the to-be-cut display panel in the target cutting region.

Method for manufacturing display panel, display panel and to-be-cut display panel

The present disclosure provides a method and time synchronization node for enabling extended holdover time. The method comprises: detecting whether the TS node loses time synchronization with its master TS node or not; and transmitting a first announce message comprising a first indicator to one or more slave TS nodes in response to detecting that the TS node loses the time synchronization with its master TS node, wherein the first indicator indicates a holdover time budget for enabling extended holdover time at the one or more slave TS nodes.

Method and time synchronization (TS) node for enabling extended holdover time

A driving method of a display panel and a display apparatus provided by embodiments of the present disclosure include: when a display mode switching startup instruction is received, a non-counting state is entered. The display panel is driven to display a first set picture, and a current display mode is switched to a target display mode. When a data mode switching completing instruction is received, a counting state is entered.

Driving method of display panel and display apparatus

Disclosed are a driving method of a display panel and a display device. The driving method of the display panel includes: obtaining display data of a current display frame (S); and inputting a data voltage to a data line according to the display data, so that the corresponding data voltages are charged into sub-pixels electrically connected to the data line (S), where the data voltages inputted on the data line are divided into a plurality of voltage groups, each voltage group includes at least two adjacent data voltages, the polarities corresponding to the data voltages in a same voltage group are the same, the polarities corresponding to the data voltages of the two adjacent voltage groups inputted into a same data line are different, and the polarities of the corresponding voltage groups on the two adjacent data lines are different.

Driving method of display panel and display device

The present disclosure discloses a lithium-manganese rich material and a preparation method and a use thereof.

Lithium-manganese rich material, preparation method therefor and use thereof

Provided is a gate driving circuit. The gate driving circuit includes a plurality of first transistors; wherein at least one first target transistor of the plurality of first transistors includes a first light-shielding layer disposed on a side of a base substrate, the first light-shielding layer being made of a conductive material; and a first gate metal layer and a first source/drain metal layer disposed on a side of the first light-shielding layer away from the base substrate; wherein the first light-shielding layer is connected to the first gate metal layer.

Gate driving circuit and manufacturing method therefor, array substrate, and display device

Techniques for compressing a data block involve adding a compression flag to a data block after the data block is decompressed by a protocol layer, the compression flag indicating that the data block is compressible or uncompressible. Such techniques further involve acquiring the compression flag of the data block. Such techniques further involve determining, in response to the compression flag of the data block indicating that the data block is compressible, to perform inline compression on the data block. Such techniques further involve preventing, in response to the compression flag of the data block indicating that the data block is uncompressible, the inline compression from being performed on the data block.

Method, electronic device, and computer program product for compressing data block

A display substrate includes a driving circuit layer arranged on a base and a light emitting structure layer arranged on one side, away from the base, of the driving circuit layer; the light emitting structure layer includes an anode, a pixel definition layer, an organic light emitting layer, a cathode, and an auxiliary electrode; the pixel definition layer has a first pixel opening exposing the anode and a second pixel opening exposing the auxiliary electrode; the organic light emitting layer connected to the anode and the cathode connected to the organic light emitting layer are arranged in the first pixel opening; the organic light emitting layer separated from the auxiliary electrode and the cathode located on one side, away from the base, of the organic light emitting layer are arranged in the second pixel opening; and the cathode is connected to the auxiliary electrode in the second pixel opening.

Display substrate and preparation method thereof, and display apparatus

A thin film transistor, including: at least one active layer pattern including a first conductive pattern, a second conductive pattern, and a semiconductor pattern; a gate on a side of the active layer pattern; a first electrode and a second electrode on a side of the gate away from the active layer pattern, and respectively electrically connected with the first conductive pattern and the second conductive pattern, a conductive shielding pattern is provided corresponding to the semiconductor pattern in at least one active layer pattern, the conductive shielding pattern is on a side of the semiconductor pattern away from the gate and is electrically connected with the first electrode, and a buffer layer is between the conductive shielding pattern and the semiconductor pattern; an orthographic projection of the conductive shielding pattern on a plane where the semiconductor pattern corresponding thereto is located at least partially covers the semiconductor pattern corresponding.

Thin film transistor, method for manufacturing the same, shift register and gate driving circuit

The present disclosure relates to a clock distribution method and apparatus in a network. The method performed at a first clock distribution apparatus comprises: determining (S) whether the first clock distribution apparatus is in a lock state; and transmitting (S), to a second clock distribution apparatus, a first announce message when the clock distribution apparatus is not in the lock state; wherein the first announce message is generated based on a default configuration about a local clock state of the first clock distribution apparatus. According to embodiments of the present disclosure, the clock distribution apparatus may generate first announce messages based on a local clock state of the clock distribution apparatus. Thus, a downstream apparatus which receives the first announce messages may avoid selecting an unstable/unlocked clock distribution apparatus as the best master, based on the local clock state of the clock distribution apparatus.

Clock distribution method and apparatus in network

Growing community of inventors

Beijing, China

Ming Wang