Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Tung Wu

Yuan-Chih Hsieh

Chia-Shiung Tsai

Lan-Lin Chao

Hsun-Chung Kuang

Tung-He Chou

Ping-Yin Liu

Li-Cheng Chu

Hung-Hua Lin

Jung-Huei Peng

Sheng-Chau Chen

Shang-Ying Tsai

Hsin-Ting Huang

Yao-Te Huang

Martin Liu

Richard Chu

Xin-Hua Huang

Chun-Kai Lan

In some embodiments, the present disclosure relates to an integrated chip fabrication device. The device includes a stealth laser apparatus arranged over a chuck configured to hold a substrate. An infrared camera is arranged over the chuck and configured to detect an alignment mark below the substrate. The alignment mark is used to align the stealth laser apparatus over the chuck. Control circuitry is configured to operate the stealth laser apparatus to form a stealth damage region at a location within the substrate that is determined based upon the alignment mark. The stealth damage region separates an inner region of the substrate from an outer region of the substrate.

Integrated aligned stealth laser for wafer edge trimming process

In some embodiments, the present disclosure relates to a method that includes aligning a stealth laser apparatus over a wafer using an infrared camera coupled to the stealth laser apparatus. The stealth laser apparatus is used to form a stealth damage region within the wafer that is continuously connected around the wafer and separates an inner region from an outer region of the wafer. The stealth damage region is also arranged at a first distance from an edge of the wafer and extends from a first depth to a second depth beneath a top surface of the wafer. Further, the method includes forming a groove in the wafer to separate the outer region from the inner region of the wafer. The outer region of the wafer is removed using a blade, and a top portion of the inner region of the wafer is removed using a grinding apparatus.

Integrated aligned stealth laser with blade and grinding apparatus for wafer edge trimming process

In some embodiments, the present disclosure relates to method for trimming and cleaning an edge of a wafer. The method includes trimming an outer edge portion of the wafer with a blade along a continuously connected trim path to define a new sidewall of the wafer. The trimming produces contaminant particles on the wafer. Further, the method includes applying deionized water to the new sidewall of the wafer with water nozzles to remove the contaminant particles. The method also includes applying pressurized gas to the wafer at a first top surface area of the wafer with an air jet nozzle. The pressurized gas is directed outward from a center of the wafer to remove remaining contaminant particles. The applying of deionized water and the applying of pressurized gas are performed in a same chamber as the trimming.

Particle prevention in wafer edge trimming

A wafer carrier assembly includes a wafer carrier and a fluid passage. The wafer carrier comprises a retainer ring confining a wafer accommodation space. The fluid passage is inside the wafer carrier. The fluid passage includes an inlet and at least an outlet to dispense fluid into the wafer accommodation space.

Wafer carrier assembly

In some embodiments, the present disclosure relates to a wafer trimming and cleaning apparatus, which includes a blade that is configured to trim a damaged edge portion of a wafer, thereby defining a new sidewall of the wafer. The wafer trimming and cleaning apparatus further includes water nozzles and an air jet nozzle. The water nozzles are configured to apply deionized water to the new sidewall of the wafer to remove contaminant particles generated by the blade. The air jet nozzle is configured to apply pressurized gas to a first top surface area of the wafer to remove the contaminant particles generated by the blade. The first top surface area overlies the new sidewall of the wafer.

A planarization apparatus is provided. The planarization apparatus includes a platen, and a grinding wheel. The platen is configured to support a wafer. The grinding wheel is over the platen and configured to grind the wafer. The grinding wheel includes a base ring, and a plurality of grinding teeth mounted on the base ring. The plurality of grinding teeth includes a plurality of grinding abrasives, and the plurality of grinding abrasives is ball type.

Planarization apparatus and planarization method thereof

An apparatus for chemical mechanical polishing includes a pad conditioner. The pad conditioner includes a first disk having a first surface and a second disk having a second surface. The first surface has a first plurality of abrasives with a first mean size and the second surface has a second plurality of abrasives with a second mean size greater than the first mean size.

Apparatus of chemical mechanical polishing and operating method thereof

A biological sensing structure includes a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to the top surface. The biological sensing structure includes a first light reflecting layer over the top surface and the sidewall surface of the mesa. The biological sensing structure includes a filling material surrounding the mesa, wherein the mesa protrudes from the filling material. The biological sensing structure includes a stop layer over the filling material and a portion of the first light reflecting layer. The biological sensing structure includes a second light reflecting layer over a portion of the stop layer and a portion of the top surface of the mesa. The biological sensing structure includes an opening in the second light reflecting layer to partially expose the top surface of the mesa.

Biological sensing structures

The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

Semiconductor having a high aspect ratio via

A wafer grinding system includes a robot arm having a suction board at one end and a table within reach of the robot arm. An upper surface of the table has a vacuum surface for sucking and holding wafers. A pusher coupled to the robot arm extends about the periphery of the suction board. The pusher flattens wafers against the upper surface of the table, allowing the table to hold by suction wafers that would otherwise be too bowed to be held in that way. Additionally, a table can have a vacuum area that is small in comparison to the wafers, which is another way of increasing the magnitude of wafer bow that can be tolerated. A grinding system can use the reduced vacuum area concept to allow the positioning table to hold bowed wafers and the pusher concept to allow the chuck tables to hold bowed wafers.

Transfer module for bowed wafers

The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding site is recessed from the first surface. Thus, a top surface of the bond pad may lie below the plane of the top surface of the substrate. A device with recessed connective element(s) (e.g., bond pad) is also described. In further embodiments, a protective layer is formed on the recessed connective element during dicing of a substrate.

MEMS device and method of formation thereof

A method of forming of biological sensing structures including a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A first light reflecting layer is deposited over the top surface and the sidewall surface of each mesa. A filling material is formed over a first portion of the first light reflecting layer. A stop layer is deposited over the filling material and a second portion of the first light reflecting layer. A sacrificial layer is formed over the stop layer and is planarized exposing the stop layer. A first opening is formed in the stop layer and the first light reflecting layer. A second light reflecting layer is deposited over the first opening. A second opening is formed in the second light reflecting layer.

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Hsinchu, Taiwan

Ming-Tung Wu