Century Technology (Shenzhen) Corporation Limited

Ming-Tsung Wang

Chih-Chung Liu

Yi-Hsiu Cheng

Meng-Chieh Tai

Kuo-Chieh Chi

Jian-Xin Liu

Li-Fang Wang

Wen-Qiang Yu

Hui Xing Wang

Yuan Xiong

Qi Xu

Lin Li

Dan Chen

De-Jiun Li

Ning Fang

Zhi-Wei Ye

Zhi-Hong Chang

Chia-Hua Huang

Wen-Lin Mei

Yang Zhao

Jing Zhu

Wen-Lin Chen

Xiao-Qian Wang

A method for repairing a white defect of a LCD panel includes providing a substrate, the substrate defining pixel areas which themselves comprise a base, a first metal layer, a first insulating layer, a semi-conductor layer, an ohmic contact layer, a source electrode, a drain electrode, and a second insulating layer; forming a through hole by laser in the second insulating layer, the through hole extending through the second insulating layer and separating the drain electrode into two spaced parts; forming a third insulating layer to cover the first conductive layers, the second insulating layer and the though hole and forming a second conductive layer by laser on the third insulating layer to couple the first conductive layer to the second conductive layer.

Display panel, active matrix substrate, and method for repairing white defect of display panel

Display panel, active matrix substrate , and method for repairing white defect of display panel

A gate driving circuit which allows narrower framing of a display screen includes cascade-connected gate driving modules. Each gate driving module is electrically coupled to first and second scan lines and outputs scanning signals to the first and the second scan lines in a time-division manner in response to first and second clock signals. Each gate driving module includes an input transistor, and first and second output transistors. The input transistor receives a trigger signal for activating the gate driving module. The input transistor controls the first output transistor to output first scanning signal to first scan line in response to the first clock signal and controls the second output transistor to output second scanning signal to the second scan line in response to the second clock signal.

Gate driving circuit

A gate driver with reduced voltage fluctuations driving a display device generates pulse signals shifted in a specified phase. The gate driver includes connected unit circuits. Each unit circuit includes an output terminal, input and output transistors, and a holding module. First and second control signals, alternating oppositely between high and low states, govern the two transistors. The input transistor is controlled by a first control signal and outputs a high level voltage to a first node based on a trigger signal. The output transistor outputs the shifted pulse signal synchronously with a clock control signal, based on the high level voltage of the first node. Initially, the trigger signal is low and the first and second control signals are high. The holding module outputs the low level voltage to the output terminal based on the first control signal and the second control signal.

Gate driver and display apparatus thereof

A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source integrated circuit, a number of data lines extending from the source integrated circuit for transmitting data signals, a number of pixel electrodes for receiving the scan signals and the data signals, and a number of transistors each electrically coupled to a corresponding scan line, a corresponding data line, and a corresponding pixel electrode. The transistors each include a gate electrode, a source electrode, and a drain electrode. The drain electrode includes an overlapping portion overlapping with the gate electrode. The gate integrated circuit transmits the scan signals along the scan lines. A size of the overlapping portion increases along a transmitting direction of the scan signal along the scan line.

Display panel structure

A thin film transistor array substrate with always-equal parasitic capacitances for a display includes scan lines, data lines, common lines, and pixel units. First and second scan lines extend in a first direction. Data and common lines extend in a second intersecting direction and are arranged to alternate in the first direction. First and second sub-pixels of pixel units are distributed on either side of and connected to one of a scan line pair. The first and second sub-pixels also straddle and connect to one data line. Bridges on a common line cover a portion of one scan line pair in the second direction and each bridge overlaps first and second scan lines. First scan line overlap with bridge is equal to second scan line overlap. A display panel using the thin film transistor array substrate is also provided.

Thin film transistor array substrate and display panel

A display device includes a display area and a peripheral area surrounding the display area. The display device includes a thin film transistor substrate, a plurality of thin film transistors, a first common line, and a storage capacitor line. The first common line, the storage capacitor, and a gate electrode of the thin film transistor are located in a same layer. The first common line is directly electrically coupled to the storage capacitor line.

Thin film transistor substrate and display device using same

A display panel includes a substrate, a plurality of thin film transistors (TFTs), a plurality common electrodes, a plurality of common electrode lines, a plurality of coupling electrodes, and a plurality of pixel electrodes. Each of the TFTs comprises a gate, a source, a drain and a channel layer coupling the source to the drain. The gate, the common electrodes, and the common electrode lines are formed on a surface of the substrate and are separated from each other. Each of the coupling electrodes couples a corresponding common electrode to a corresponding common electrode line, and a space is defined between the corresponding common electrode and the corresponding common electrode line.

Display panel and manufacturing method thereof

An array substrate includes a display area, an edge area, data lines, pixel units, a feedback transmission line, a feedback control circuit, and a display drive circuit. The edge area surrounds the display area. The feedback transmission line, the feedback control circuit, and the display drive circuit are spatially corresponding to the edge area. The feedback transmission line electrically connects at least one of the data lines and the feedback control circuit. The feedback transmission line detects a data signal transmitted by the data lines and outputs a feedback signal to the feedback control circuit. The feedback control circuit outputs a common voltage to the display drive circuit according to the feedback signal. The display drive circuit outputs the common voltage to the pixel units.

Array substrate and liquid crystal display device having same

An active array matrix substrate of a display panel includes a number of scan lines parallel to each other and arranged in a first metal layer of a first substrate, a number of data lines parallel to each other and arranged in a second metal layer of the first substrate, a number of gate electrodes arranged in the first metal layer, a number of source electrodes arranged in the second metal layer, and a number of drain electrodes arranged in the second metal layer. The source electrode includes at least one source extending portion spaced from and configured to overlap with the first metal layer. The drain electrode includes at least one drain extending portion spaced from and configured to overlap with the first metal layer.

Active array matrix substrate of display panel

An array substrate can include a plurality of thin film transistors, a plurality of function lines, a plurality of leads, a coupling part and a driver. The plurality of function lines are configured to transmit driving signals to the thin film transistors. The plurality of leads include a first lead and a second lead. The coupling part is electrically coupling the leads to the function lines. The driver is electrically coupled to the leads, and configured to provide the driving signals to the function lines. The first lead has a length larger than that of the second lead. A contacting area between the first lead and the coupling part is larger than that between the second lead and the coupling part. A display panel with the array substrate is also provided.

Array substrate and display panel with same

A TFT array substrate for a TFT LCD includes a plurality of pixels each consisting of a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel arranged in a 2&#xd7;2 matrix. Two data lines are located between each two neighboring columns of the sub-pixels. A scan line is located between two neighboring rows of the sub-pixels. The sub-pixels are driven by column inversion. The scan lines in electrical connections with different rows of the pixels are turned on successively along a vertical direction. Two neighboring same colored sub-pixels in a same row of the sub-pixels have opposite polarities and two neighboring same colored sub-pixel in a same column of the sub-pixels respectively have the same polarity when the TFT LCD is operated to output a screen having a color the same as the color of the two neighboring same colored sub-pixels.

RGBW TFT LCD having reduced horizontal crosstalk

A thin film transistor array substrate includes a base, a first metal layer having a gate electrode and a first insulating layer covering the base and the first metal layer. A semiconductor layer is formed on the first insulating layer facing but insulated from the gate electrode. The first insulating layer also supports a second metal layer having a source electrode and a drain electrode. A pixel electrode layer is electrically coupled to the source electrode or the drain electrode. A common electrode layer is insulated from the pixel electrode and is configured to receive a common voltage. A transparent conductive layer is formed on the base and is insulated from the pixel electrode. The semiconductor layer, electrically coupled to the source electrode and the drain electrode, is located between the source electrode and the drain electrode.

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Taipei, Taiwan

Ming-Tsung Wang