United Microelectronics Corp.

Ming-Tsung Tung

Chin-Hung Liu

Jung-Ching Chen

Chien-Ming Lin

Chin-Lung Chen

Anchor Chen

Jui-Hsiang Pan

Hwi-Huang Chen

Chih-Hung Lin

Jih-Wei Liou

Wen-Kuo Li

Chun-Ching Yu

A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region.

LDMOS with N-type isolation ring and method of fabricating the same

A method for forming a depletion-mode single-poly electrically erasable programmable read-only memory (EEPROM) cell is provided. The method includes providing a substrate having a floating region and a control region. Then, an isolation deep well and a deep well are formed in the floating region and the control region of the substrate respectively. A well region is formed in the isolation deep well simultaneously with forming an isolation well region between the isolation deep well and the deep well in the substrate. A depletion doped region and a cell implant region are formed at the well region of the substrate and the deep well of the substrate respectively. A floating gate structure is formed across over the floating region and the control region. An implantation process is performed to form a source/drain region and a heavily doped region in the depletion doped region and the cell implant region respectively.

Depletion-mode single-poly EEPROM cell

An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length 'A' extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length 'L' extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values.

IC chip

A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance 'd' away from the gate electrode.

High voltage metal-oxide-semiconductor transistor devices and method of making the same

A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.

High-voltage device structure

The present invention provides a method of forming a lateral diffused metal-oxide semiconductor (LD MOS) transistor on a semiconductor wafer. An ion implantation process is performed on a predetermined area of the silicon substrate so as to form a p-well adjacent to an n-well. An insulation layer is then formed on a predetermined area of the n-well. A gate layer is formed on a portion of the p-well and the n-well, and one side of the gate layer is positioned on the surface of the insulation layer. Finally, an ion implantation process is performed to form two n-type doped regions on the p-well and the n-well. The two doped regions are used as the source and the drain of the LD MOS transistor.

Method of forming a lateral diffused metal-oxide semiconductor transistor

The present invention provides a method for forming a transistor with a gradient doped source/drain. The method comprises the following steps. First, two first N-wells are formed in a substrate and the first N-wells are separated in both sides of the substrate. The, two second N-wells are formed in the substrate and the second N-wells overlie the first N-wells. An implanting concentration of first N-wells is smaller than an implanting concentration of second N-wells. Next, a field oxide region is formed in the substrate between the first N-wells and the field oxide region overlies on a portion of second N-wells. Thereafter, portion of the field oxide region and the substrate are removed to form a trench n the substrate, wherein the remaining field oxide region overlies on the second N-wells. Next, a gate oxide layer is formed on a bottom surface and sidewall of the trench. Then, a polysilicon gate is formed on the substrate. The trenches filled with the polysilicon gate and the polysilicon gate overlies a portion of the remained field oxide region. Last, a N -type source/drain is formed in the substrate and the N -type source/drain is adjacent to the remaining field oxide region and overlies the second N-wells.

Forming complementary metal-oxide semiconductor with gradient doped source/drain

A method for fabricating an HVMOS transistor that can reduce snapback is disclosed. The semiconductor wafer comprises an N-type silicon substrate, and a P-type epitaxial layer formed on the surface of the silicon substrate. The HVMOS transistor comprises a first P-well region formed within the epitaxial layer, a second P-well region formed within the first P-well region a source region formed within the second P-well region, an N-drain region formed in the epitaxial layer, a gate, and an N-type diffused region formed both in the epitaxial layer and in the silicon substrate. The diffused region is under the first P-well region and overlaps the first P-well region.

High-voltage metal-oxide-semiconductor transistor

A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers. A source region with the second conductive type and a drain region with the second conductive type are respectively located in the third and the second well regions exposed by the gate structure and the field oxide layers.

High-voltage device and method for manufacturing high-voltage device

A method for forming a laterally diffused metal-oxide semiconductor is disclosed. The invention normally is for forming a transistor device, which includes the following steps. Firstly a semiconductor layer is provided. Then a field insulating region is formed into the semiconductor layer. Sequentially forming a gate dielectric layer over a portion of the field insulating region is carried out. Then forming a deep portion of a first drain/source region within the semiconductor layer and spaced from the field insulating region/the top surface. Here, the deep portion is doped with dopants of a conductivity type, with the deep portion having a first doping concentration. The next step is forming a lightly doped portion of the first drain/source region within the semiconductor layer and a neighbouring portion of the field insulating region/the oxide top surface and adjacent the channel region. Generally the lightly doped portion is doped with dopants of the conductivity type. And there is a second doping concentration which is less than the first doping concentration. A main portion of said first drain/source region within the semiconductor layer is formed. Therefore the main portion neighbors the field insulating region/the oxide top surface and is adjacent the lightly doped portion. Also, the main portion disposed above the deep portion as well as main portion is doped with dopants of the conductivity type and has a third doping concentration, which is less than the first doping concentration and is greater than the second doping concentration. Then a second drain/source region is formed within the semiconductor layer and spaced from the lightly doped portion of the first drain/source region by a channel region, the second drain/source region is doped with dopants of the conductivity type. Finally the process for forming a gate electrode over at least a portion of the channel region and insulated is carried out therefrom.

Producing laterally diffused metal-oxide semiconductor

A method for fabricating high voltage semiconductor devices having a gradient doping of a drift region which comprises N-well 1 and N-well 2 with two different doping densities. This method results in the lift in device's current drive capability and as well as its breakdown voltage. The method further comprises forming a buried spacer oxide, serving as a point of exertion for the edges of the buried gate electrode. And finally, the extension in channel length and the placement of both the channel and drift regions change to vertical direction, all of those result in a greater reduction in the occupied chip area. These advantages attribute to the formation of a buried gate electrode by trench etching method.

Forming high voltage complementary semiconductor device (HV-CMOS) with gradient doping electrodes

The method of the present invention comprises the following steps. First, a silicon oxide layer is formed on a semiconductor substrate. Then, a first doping N-well region is formed in the semiconductor substrate. Next, a second doping N-well region which overlies the first doping N-well region is formed in the semiconductor substrate. Thereafter, a trench isolation is formed into the semiconductor substrate having a depth less than the depth of the first doping N-well region. Then, the silicon oxide layer is removed. Next, a field oxide is grown on the surface at a bottom of the trench. Then, a third N doping region is formed along the entire surface of the pad oxide layer within the trench. Next, the field oxide layer is removed to expose the semiconductor substrate within the trench. Thereafter, a gate oxide layer is formed onto the surface of a semiconductor layer with the trench. Next, an N-type polysilicon layer is formed to fill the trench. Last, an N,source/drain layer is formed which is located above the second doping N-well region and under the top surface of the semiconductor substrate in order to complete the laterally diffused metal-oxide semiconductor structure.

Formation of laterally diffused metal-oxide semiconductor device

A method of forming an improved bipolar junction device structure. By forming a well region around the emitter terminal, the area of distribution of ions within the emitter terminal of a vertical bipolar junction transistor is enlarged. Furthermore, by forming a separate well region around the emitter terminal and the collector terminal, the area of distribution of ions within the emitter terminal and the collector terminal of a lateral bipolar junction transistor is also enlarged.

Method for manufacturing a bipolar junction device

A structure for forming a laterally diffused metal-oxide semiconductor is disclosed. The structure will include the following portions. They are a semiconductor layer with a conductivity type, a field insulating region into the semiconductor layer, a gate electrode formed over at least a portion of a channel region and insulated therefrom. The first drain region without an oxide top surface is formed beside one side of the gate electrode into the semiconductor layer. A second drain region is formed in the semiconductor layer. Also, a lightly doped portion borders the channel region and the neighbouring field insulating region. The main portion neighbors the oxide top surface and is spaced from the channel region by the lightly doped portion. The main portion has a second doping concentration that is less than the first doping concentration. The deep portion has a third doping concentration that is less than the second doping concentration.

Growing community of inventors

Hsin-Chu, Taiwan

Ming-Tsung Tung