Yield Microelectronics Corp.

Ming-Tsang Yang

Ya-Ting Fan

Hsin Chang Lin

Chia-Hao Tai

Yang-Sen Yen

Wen-Chien Huang

Hsin-Chang Lin

Cheng-Ying Wu

Hao-Cheng Chang

A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines.

Low-voltage EEPROM array

An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit line and a second group bit line; the word line includes a first word line; and the common source lines include a first common source line. In addition, a plurality of sub-memory arrays are provided. Each sub-memory array contains a first, second, third, and fourth memory cells. Wherein, the first and second memory cells are symmetrically arranged, and the third and fourth memory cells are symmetrically arranged; also, the first and second memory cells, and the third and fourth memory cells are symmetrically arranged with the first common source line as a symmetric axis.

Area saving electrically-erasable-programmable read-only memory (EEPROM) array

A cost saving EEPROM array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines contain a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line.

Cost saving electrically-erasable-programmable read-only memory (EEPROM) array

A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

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Hsinchu County, Taiwan

Ming-Tsang Yang