Bell Communications Research, Inc.

Graphics Communication Technologies, Ltd.

Ming-Ting Sun

Kou-Hu Tzou

Ting-Chung Chen

Shaw-Min Lei

Hiroshi Fujiwara

Kun-Min Yang

Lancelot Wu

Akio Shimatzu

Alexander C Loui

Ming-Lei Liou

Toshifumi Sakaguchi

An apparatus and method for combining video signals from multiple users in a continuous presence video conferencing system. Video signals are received from each of a number of different system users. The signals include input frames each having a number of different groups-of-blocks (GOBs). The GOBs correspond to hierarchically organized video data and header information. The input frame GOBs are used to form a composite output video signal suitable for transmission to each of the system users. An output frame of the composite output signal incorporates at least one of the GOBs from the input frames of each of the users and less than all of the GOBs from the input frame of at least one of the users. The resulting output video signal provides flexible continuous presence video conferencing in which video signals from multiple users may be simultaneously displayed to all users in a selected divided-screen format. The input frames may be Quarter Common Intermediate Format (QCIF) frames and the output frames may be Common Intermediate Format (CIF) frames in accordance with the H.261 video coding standard.

Group-of-block based video signal combining for multipoint continuous

Four QCIF video input signals generated by participants in a multiparty video conference are combined in the coded domain to produce a merged CIF video output signal. When the CIF video output signal is transmitted back to each party's video terminal, a combined 2.times.2 image is displayed. A video signal combiner (700) combines the input video signals in the coded domain by time-division multiplexing the inputs at the GOB level. In order to maintain frame synchronization between the inputs which may be arriving at different frame repetition rates, the combiner stores the inputs in buffers (706-709) and processes (710) the temporal reference (TR) numbers associated with each frame in each input before merging the GOBs from each input in accordance with the processed TR number. Specifically, the TR of each input is offset by an initial TR number associated with each input and determined at turn-on. The offset TR in each input is then mapped onto a scale of TR numbers that is common to each input. The each output frame is formed by time-division multiplexing GOBs from the inputs that have the same offset and mapped TR number. Only GOB headers and empty data fields are inserted into the combined data stream for those inputs not having a frame with that same mapped TR number.

Continous presence video signal combiner

A variable-length codeword encoder is disclosed which produces 8-bit output segments for storage in a buffer (23) for subsequent transmission over a transmission channel (24). The encoder includes two memory tables (15, 16), which produce in response to each input symbol to be encoded, a variable-length codeword and an a codeword length. An accumulator (31, 33) accumulates, modulo-8, the successive codeword lengths, producing a carry signal during any clock cycle in which eight or more bits codeword bits are accumulated. At each clock cycle, the variable-length codeword is input to the parallel inputs of a cross bar shift control circuit (30). This shift control circuit produces a 16-bit output in which the input word is embedded. The input word is shifted in the 16-bit output from the more significant bit positions to the less significant positions by a shift value determined from previous accumulated codeword lengths, with the shift value number of '0' bits being inserted in the more significant bit positions preceding the codeword. An OR circuit (38) combines the shifted variable-length codeword with previous variable-length codeword bits to form a concatenated sequence which is stored in upper and lower latches (53, 54). At any clock cycle, when the number of accumulated codeword bits is less than eight, the concatenated bits stored in the first and second latches are fed back to the OR circuit for combination at the next clock cycle with the next shifted variable-length codeword. When eight or more codeword bits are accumulated, the accumulator produces a carry signal and the 8-bit segment in the upper latch is outputted. The 8-bits in the lower latch are then shifted to the more significant bit positions of a concatenated sequence that is fed back to the OR circuit for combination with the next shifted variable-length codeword.

Variable-length codeword encoder

Method and system for high order conditional entropy coding utilizing an incremental-tree-extension technique to design a conditional tree for the coding. For complexity reduction, code table reduction and non-uniform quantization of conditioning symbols or pixels is provided. A pattern matching technique is provided for fast conditioning state extraction, and a multistage pipelined structure is provided to handle the case of a large number of conditioning pixels. Using the complexity reduction techniques and the hardware structures, it is possible to implement practical high order conditional entropy codecs using current low-cost VLSI (Very Large Scale Integration) technology.

Method and system for high order conditional entropy coding

A variable-length decoder is disclosed which includes a decoder part (101) and an interface part (102). The decoder part includes two decoder latches (110 and 111) which store consecutive sequences of bits, which are each equal in length to the maximum-length codeword. A decoder barrel shifter (109) provides an output decoding window of a subsequence of bits in the two latches equal in length to the maximum-length codeword. This subsequence is supplied to a memory device (116) which provides a corresponding decoded codeword output and codeword-length output for each subsequence that begins with the first bit of a variable-length to be decoded. At each clock cycle, the same subsequence is supplied to the input of the first decoder latch and the decoder barrel shifter is shifted by the codeword-length of the previous word so that the decoder barrel shifter output subsequence always begins with the first bit of the word to be decoded. The interface part supplies the second decoder latch. The interface part includes an interface barrel shifter (127) which is supplied from two interface latches (125 and 126) which in turn are provided input from a buffer (106) which stores the input bit stream in fixed-length segments. An accumulator (130, 131) accumulates the codeword-lengths of decoded codewords and, at each clock cycle, shifts the output of the interface barrel shifter in accordance with the accumulated lengths so that the bits in its output window are consecutive with the bits in the output window of the decoder barrel shifter. When the accumulated codeword-lengths indicate that all the bits in the first interface latch have been transferred to the decoder part, then a new segment is retrieved from the buffer and stored in the second interface latch while the previous segment in that latch is transferred into the first interface latch.

High-speed variable-length decoder

A variable-length decoder is disclosed in which a received variable-word-length encoded bit stream is input to a buffer (102) and read out in parallel sequences equal in length to the maximum length codeword. These sequences are read into cascaded latches (105, 107). The cascaded sequences in both latches are input to a barrel shifter (109) which provides from its multi-bit input, a sliding decoding window to a table-lookup memory device (112). A control signal directly shifts the position of the decoding window of the barrel shifter as each codeword is detected. To detect each codeword, the initial bits in the decoding window are compared with the codeword entries in the table-lookup memory. When a codeword is detected, the corresponding stored codeword length is accumulated (120) with previously accumulated codeword lengths to produce the control signal which directly shifts the decoding window by the number of bits in the just decoded word. When all the bits in the first latch have been decoded, the next bit sequence in the buffer is input to the second latch while the previous bit sequence in the second latch is transferred to the first latch. The decoding window is then adjusted to the beginning of the next undecoded sequence.

High-speed flexible variable-length-code decoder

This processor is capable of real time processing of blocks of video pixel or other two-dimensional data to yield the two-dimensional Discrete Cosine Transform (DCT) thereof. The processor can be used as part of a video bandwidth or image compression system. The circuitry comprises a first one-dimensional DCT processor which simultaneously computes an entire row or column of vector inner products by using distributed arthmetic and using decimation-in-frequency to reduce the amount of memory capacity (ROM) required. Partial sums may also be used to further reduce ROM size. The one-dimensional transformed matrix from the first processor is stored in a transposition memory and the transpose of the stored matrix is applied to a second one-dimensional DCT processor of similar circuitry which computes the desired two-dimensional DCT of the input data matrix.

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Holmdel, NJ, United States of America

Ming-Ting Sun