Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Te Chen

Chia-Ming Tsai

Chandrashekhar Prakash Savant

Tien-Wei Yu

Chun Hsiung Tsai

Shao-Hua Wang

Sheng-Wei Lee

Hsing-Jui Lee

Yi-Hann Chen

Chia-Yi Chuang

Shih-Chi Lin

Cheng-Hung Hu

Zack Chong

Shiu-Ko JangJian

Cheng-Ta Wu

Ting-Chun Wang

Chung-Ren Sun

Tsun-Jen Chan

Jung-Wei Lee

Ta-Hsiang Kung

Kin Shun Chong

Kun-Hsiang Lin

Kang Hua Chang

Lee-Te Tseng

Chih-Hsien Ou

Jun-Jie Cheng

Kuo-Feng Yu

Joung-Wei Liou

Chia-Hui Lin

Szu-An Wu

Shao-Yen Ku

Jun He

Chien-Feng Lin

Pei-Wei Lee

Ching-Hua Lee

Shang-Yuan Yu

Miao-Syuan Fan

Li-Chung Wang

Tzu-Yang Chung

Wen-Shan Chang

Chi-Fu Yu

Hsiao Chien-Wen

Da-Hsiang Chou

Cheng-Chia Kuo

Shan-Ching Lin

Ying-Hsiu Tsai

Jung-Chang Chen

Kuo-Yuan Ho

Hui-Ting Tsai

Tsang-Yu Liu

Cheng-Liang Chang

Yh-Hsiu Hsiao

Yi-Jiun Lee

Kan Hwa Chang

Yin-Ping Lee

Shih-Chang Hsu

Jong-Min Lin

Kuo-Ming Yu

Kuo-Chuan Chen

The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

Gate stack treatment

A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.

Semiconductor structure and manufacturing method of the same

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Method of manufacturing semiconductor devices and semiconductor devices

A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.

FinFET gate structure

A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.

Method of manufacturing a semiconductor device and a semiconductor device

Method of manufacturing semiconductor devices using a capping layer in forming gate electrode and semiconductor devices

An atomic layer deposition apparatus includes a chamber including a plurality of regions; and a heating device respectively providing specific temperature ranges for the plurality of regions. By flowing precursor gases at different flow rates in the different regions, thin films can be simultaneously formed in the different regions having different film thicknesses.

Atomic layer deposition method

An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.

Contact resistance reduction technique

An ion implantation apparatus and a method for ion implantation provides for implanting multiple substrates simultaneously. The different substrates are on corresponding platens within an ion implantation chamber or they may be positioned on separate substrate holders on a single oversized platen. The substrates and platen or platens, are translatable with respect to an ion beam, the individual substrates are rotatable and the position of the substrates relative to one another in the ion implantation chamber are movable. By rotating, translating and repositioning substrates during the ion implantation process, the entirety of all substrates are implanted by an ion beam even when the ion beam has a relatively small footprint and a relatively short scan length, compared to the diameters of the substrates undergoing implantation.

Multi-platen ion implanter and method for implanting multiple substrates simultaneously

A system includes an implantation chamber; a warming chamber, wherein the warming chamber is outside of the implantation chamber and has a sidewall shared with the implantation chamber; a first robotic arm configured to move a first wafer from the implantation chamber into the warming chamber; and a second robotic arm configured to move a second wafer into the implantation chamber.

High-throughput system and method for post-implantation single wafer warm-up

An ion beam generator includes a plurality of arc chambers, wherein each arc chamber of the plurality of arc chamber is integral with every arc chamber of the plurality of arc chambers. The ion beam generator further includes a plurality of extraction slits, wherein each extraction slit of the plurality of extraction slits is configured to extract ions from a corresponding arc chamber of the plurality of arc chambers. The ion beam generator further includes a plurality of arc slits, wherein each arc slit of the plurality of arc slits is configured to provide an ion path between a corresponding extraction slit of the plurality of extraction slits and the corresponding arc chamber of the plurality of arc chambers.

Ion beam generator, ion implantation apparatus including an ion beam generator and method of using an ion beam generator

Growing community of inventors

Hsinchu, Taiwan

Ming-Te Chen