Ali Corporation

Ming-Ta Lee

Yi Chun Chen

Ching-Chung Cheng

Hsu-Che Nee

Yen Liang Lin

Chen Hsu

A signal receiver and a signal transceiver are provided, which may avoid unnecessary leakage current. The signal receiver includes a termination switch pair, a first resistor, a second resistor, and a pull-down circuit. The termination switch pair receives an operation power supply. The termination switch pair has a common control end. The first resistor is coupled between a first signal input end and the common control end. The second resistor is coupled between a second signal input end and the common control end. The pull-down circuit is coupled between the common control end and a reference voltage end. The pull-down circuit determines whether to pull down a first control voltage on the common control end to a reference voltage according to a power-on state or a power-off state of the signal receiver.

Signal receiver and signal transceiver

A phase interpolator capable of preventing a glitch from being generated during a clock signal switching operation and a clock signal selector thereof are provided. The clock signal selector includes a selector and a selection signal generator. The selector receives multiple clock signals with different phases. The selector selects one of the clock signals according to a selection signal to generate a selected clock signal. The selection signal generator is coupled to the selector and generates the selection signal. When the selector switches from selecting a first clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point according to a transition point of one of the first clock signal and the second clock signal whose phase lags behind a phase of the other, and generates the selection signal according to the set time point.

Phase interpolator and clock signal selector thereof

A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.

Deskew circuit for differential signal

The disclosure provides a bias voltage calibration circuit adapted for a signal receiving device. The bias voltage calibration circuit includes a reference voltage generator, a voltage-current converter, and a bias current generator. The reference voltage generator receives a voltage adjustment signal, and adjusts a voltage value of a generated reference voltage according to the voltage adjustment signal. The voltage-current converter is coupled to the reference voltage generator, and converts the reference voltage to generate a reference current. The bias current generator generates a plurality of bias currents according to the reference current, and provides the bias current to an equalization circuit of the signal receiving device in a calibration mode.

Signal receiving device and bias voltage calibration circuit thereof

A signal receiving device and an equalizer tuning method thereof are provided. A first equalizer receives an input signal and generates a first equalized signal by compensating the input signal according to a first equalization parameter. A second equalizer generates a second equalized signal by compensating the first equalized signal according to a second equalization parameter. A clock and data recovery circuit recovers the second equalized signal to generate an output signal. An equalizing controller receives the input signal and outputs a first control signal and a second control signal, to adjust the first equalization parameter according to the first control signal and adjust the second equalization parameter according to the second control signal. The equalizing controller detects a first pattern symbol and a second pattern symbol from the output signal and tunes the second equalization parameter according to the number of the first pattern symbol and the second pattern symbol.

Growing community of inventors

Taipei, Taiwan

Ming-Ta Lee