Alpha Omega Semiconductor Inc.

Other

Qualcomm Incorporated

Mitsubishi Electric Research Laboratories, Inc.

Hughes Network Systems, LLC

Ming Sun

Kai Chieh Liu

François Hébert

Tao Feng

Lei Shi

Xiaotian Zhang

Yueh-Se Ho

Yueh Se Ho

Leeshawn Luo

Benjamin A Werner

Xiao Meng Zhang

Demei Gong

Anup Bhalla

Jun Lu

William J Morrison

Joseph Czompo

Ning Luo

Sai Pradeep Venkatraman

Weihua Gao

Koon Hoo Teo

Zafer Sahinoglu

James C Lee

Alex Toh

Aicsa Becerril

Alfred Ebrahim

Argo Chang

Ryan Huang

Techniques provided herein are directed toward enabling on-device learning to create user-specific movement models that can be used for dead reckoning. Because these moving models are user-specific, they can be later used to identify user-specific motions in a manner that provides for a dead reckoning location estimation. In some embodiments, these models can be focused on pedestrian movement, based on the repetitive motion that occurs when a user takes a stride (walking, jogging, running, etc.) or other repetitive motion (swimming, riding a horse, etc.).

User-specific learning for improved pedestrian motion modeling in a mobile device

Techniques provided herein are directed toward resolving a direction of travel of a mobile device based on MEMS sensor data by identifying a type of motion the mobile device is subject to and offsetting vertical acceleration data with horizontal acceleration data by a predetermined time offset based on the identified type of motion. The offset vertical and horizontal acceleration data can then be used to resolve, with an increased accuracy, a direction of travel of the mobile device.

Pedestrian sensor assistance in a mobile device during typical device motions

A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.

Methods and configuration for manufacturing flip chip contact (FCC) power package

A method of assembling a satellite antenna including placing a first layer PCB including an alignment hole on an assembly fixture including an alignment pole, placing a solid foam spacer including an alignment hole on the assembly fixture, pressing the solid foam spacer onto the first layer PCB to adhere the solid foam spacer to the first layer PCB, removing an adhesive carrier film from a reflector patch of a reflector patch sheet including an alignment hole, placing the reflector patch sheet on the assembly feature, pressing the reflector patch sheet onto the solid foam spacer to adhere the reflector patch to the solid foam spacer, and removing a release liner from the top of the reflector patch sheet to remove excess material from the reflector patch sheet.

Method and apparatus for assembly of a satellite antenna

Various arrangements for determining a location of a base station without timing synchronization are presented. A mobile device may determine that it is moving faster than a threshold velocity. The mobile device may capture a first unsynchronized time of arrival (TOA) measurement and determine an associated first location, wherein the first unsynchronized TOA measurement is based on a first unsynchronized timing measurement of a first received reference signal. The mobile device may capture a second unsynchronized TOA measurement and determine an associated second location, wherein the second unsynchronized TOA measurement is based on a second unsynchronized timing measurement of a second received reference signal. Based on the mobile device moving faster than the threshold velocity, the first location, the second location, the first unsynchronized TOA measurement, and the second unsynchronized TOA measurement may be used for determining the location of the base station.

Method and apparatus for asynchrosous positioning of wireless base stations

Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

Wafer level chip scale package and process of manufacture

At least one parameter of a signal is determined, wherein the signal is a sinusoidal signal including noise, wherein the parameter includes at least one of a frequency of the signal, and an angle of a phase of the signal. The frequency of the signal is determined iteratively based on a linear relationship among the frequency of the signal, samples of the noise, and samples of the signal using a statistical correlation among the samples of the noise. During a current iteration the statistical correlation is updated based on the frequency of the signal determined during a previous iteration, and the samples of the signal are updated with values of the signal during a current period of time.

Method and system for determining parameters of sinusoidal signals

A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

Method and apparatus for ultra thin wafer backside processing

The present invention features a method for fabricating a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die.

Multi-layer lead frame package and method of fabrication

A clip for a semiconductor device package may include two or more separate electrically conductive fingers electrically connected to each other by one or more electrically conductive bridges. A first end of at least finger is adapted for electrical contact with a lead frame. The bridges are adapted to provide electrical connection to a top semiconductor region of a semiconductor device and may also to provide heat dissipation path when a top surface of the fingers is exposed. A semiconductor device package may include the clip along with a semiconductor device and a lead frame. The semiconductor device may have a first and semiconductor regions on top and bottom surfaces respectively. The clip may be electrically connected to the top semiconductor region at the bridges and electrically connected to the lead frame at a first end of at least one of the fingers.

Conductive clip for semiconductor device package

This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.

Flip chip contact (FCC) power package

The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Method for making solder-top enhanced semiconductor device of low parasitic packaging impedance

A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.

Growing community of inventors

Sunnyvale, CA, United States of America

Ming Sun