Integrated Device Technology, Inc.

Intel Corporation

Ming-Shiung Chen

Chi-Lie Wang

Jason Z Mo

Sita Rama Chandrasekhar Mallela

Han Hua Leong

Anuj Agrawal

Steve Juan

Muhammad Kazim Hafeez

An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.

Techniques for determining timestamp inaccuracies in a transceiver

A method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer (RT) and continuous transfer (CT) modes have been disclosed where outstanding packets to be processed is through a Retransmission Mapper with a VOQ read pointer realignment that can quickly optimize network traffic with multiple VCs and mixed RT/CT modes.

Method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer and continuous transfer modes

A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized.

Multi-bus structure for optimizing system performance of a serial buffer

Growing community of inventors

Santa Clara, CA, United States of America

Ming-Shiung Chen