United Microelectronics Corp.

United Semiconductor Corp.

Ming-Shing Chen

Ming-Hui Chang

Wei-Ting Wu

Chao-Chun Ning

Yu-Ting Wang

Yu-Cheng Tung

En-Chiuan Liou

Chih-Wei Yang

Nien-Chung Li

Chin-Sheng Yang

Ching Fu Chang

Wei-Chi Chen

Horng-Nan Chern

Jy-Hwang Lin

Shu-Jen Chen

Li-Shiun Chen

Yung-Chieh Kuo

Hui-Ling Huang

Chien-Ying Sun

Chorng-Lih Young

Hsin Tai

Kuen-Syh Tseng

Akira Mao

Chih-Han Chen

Ying-Chou Lai

Chao-Hsien Wu

Chia-Hui Hwang

Lu-Ran Huang

An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer and first conductive metal layer on the first polysilicon plug; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in the first ILD layer and second conductive metal layer on the second polysilicon plug.

Semiconductor image sensor device

An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer, first self-aligned silicide layer on the polysilicon plug and first conductive metal layer on the first self-aligned silicide layer; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in first ILD layer, second self-aligned silicide layer on the second polysilicon plug, and second conductive metal layer on the second self-aligned silicide layer.

Semiconductor image sensor device and fabrication method thereof

A method for fabricating flash memory is provided. A plurality of floating gate structures is formed on a gate dielectric layer in the memory device region of a substrate. The protective spacers are formed on two opposite sidewalls of each floating gate structure. A polysilicon gate structures are formed on the logic device region and a polysilicon control gate structure with an opening are formed on the memory device region to cover two adjacent floating gate structures, wherein the two protective spacers facing each other between two adjacent floating gate structures are exposed by the opening, and then the exposed protective spacer are removed. An ion implantation is performed on the substrate to form a source region between the two adjacent floating gate structures on each cell area. There will be no polysilicon material residue in the memory device region or pitting/undercutting phenomenon in the logic device region.

Method for fabricating flash memory

A planarization process includes the following steps. A first dielectric layer and a second dielectric layer are sequentially formed to conformally cover a pattern in a cell area and a substrate in the cell area and an isolation area, thereby the first dielectric layer and the second dielectric layer having a dishing in the isolation area. A dummy material is formed in the dishing and exposes a part of the second dielectric layer right above the pattern. A first removing process is performed to remove the exposed part of the second dielectric layer. The dummy material is removed. A second removing process is performed to remove an exposed part of the first dielectric layer by using the second dielectric layer as an etch stop layer. A third removing process is performed to remove the second dielectric layer and the first dielectric layer.

Planarization process

A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.

Semiconductor memory device

A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided.

Fabricating method of lateral-diffused metal oxide semiconductor device

Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

Semiconductor device and operating method thereof

Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.

Shallow trench isolation structures in semiconductor device and method for manufacturing the same

Lateral-diffused metal oxide semiconductor device and fabricating method thereof

A semiconductor device and a method of forming the same, the semiconductor device includes a plurality of fin shaped structures and a dummy gate structure. The fin shaped structures are disposed in a substrate, where at least one of the fin shaped structures has a tipped end. The dummy gate structure is disposed on the substrate, and includes an extending portion covering the tipped end.

Fin shaped semiconductor device structures having tipped end shape and method for fabricating the same

A LDMOS includes a gate structure disposed on the surface of a semiconductor substrate, a source region having a first conductivity type, a drain region having the first conductivity type, an isolation region surrounding the source/drain regions, a doped region having a second conductivity type, and a base region having the second conductivity type formed in the doped region. The source/drain regions are respectively disposed on two sides of the gate structure. The doped region surrounds the isolation region, and the bottom of the doped region is deeper than the bottom of the isolation region. The base region is disposed at the surface of the semiconductor substrate.

Lateral diffused metal-oxide-semiconductor device

Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method include steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited covering the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removing by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate selectively is removed.

A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.

Method for manufacturing MOS transistors utilizing a hybrid hard mask

A multi-film capping layer having a cobalt layer, a barrier layer, and a stuffing layer is disclosed, wherein the barrier layer isolates the cobalt layer from the stuffing layer. The multi-film capping layer is formed on a gate transistor and applicable to a self-aligned silicide (salicide) process, so that a sheet resistance of the salicide layer on conductive regions of the gate transistor is significantly reduced. The stuffing layer further prevents entry of oxygen or moisture to the salicide layer, thus no cobalt oxide is formed when RTP is performed. Without formation of the cobalt oxide, the salicide process is free from the bridging issue and the filament issue.

Multi-film capping layer for a salicide process

A method of forming a barrier layer is described. A dielectric layer is formed on a substrate. The dielectric layer comprises an opening exposing a portion of the substrate. A metallic layer, which is conformal to the opening, is formed on the dielectric layer. A first metallic nitride layer, which is conformal to the opening, is formed on the first metallic layer by chemical vapor deposition. The second metallic nitride layer, which is conformal to the opening, is formed on the first metallic nitride layer.

Growing community of inventors

Tainan, Taiwan

Ming-Shing Chen