Mediatek Corporation

Ming-Shiang Lai

Chung-Hung Tsai

Yung-Chun Lei

The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.

Command controller, prefetch buffer and methods for accessing a serial flash in an embedded system

A booting system includes: a non-XIP memory, for storing a plurality of booting images, wherein the booting images comprise a source image and a plurality of duplicates of the source image; an XIP memory, coupled to the non-XIP memory; and a code shadowing module, coupled to the non-XIP memory and the XIP memory, for shadowing a specific booting image to the XIP memory if no errors are detected when carrying out error detection (EDC) checking on the specific booting image; wherein if at least a specific part of a booting image does not pass EDC checking, the code shadowing module shadows error-free parts of the booting image to the XIP memory, carries out EDC checking on at least a duplicate of the specific part, and then shadows an error-free part corresponding to the specific part to the XIP memory.

System for booting from a non-XIP memory utilizing a boot engine that does not have ECC capabilities during booting

The invention relates to an embedded system, and in particular, to an embedded system capable of compensating setup time violation. An embedded system comprises a serial flash and an access circuit. The serial flash further comprises an input pin and an output pin. The access circuit further comprises a processor, a shift register, a serial flash controller, and a time compensator. The input pin receives an adjusted input signal and the output pin sends an output signal. The processor controls the operation of the access circuit. The serial flash controller enables an operational clock of the access circuit. The time compensator compensates a timing of the output signal by referring to the operational clock. The shift register converts data in parallel form to serial form.

Embedded system for compensating setup time violation and method thereof

A booting system is disclosed for booting from a non-XIP memory utilizing a boot engine that does not have ECC capabilities during booting. The booting system includes: a non-XIP memory for storing a boot loader code and a plurality of operation system (OS) images, wherein the OS images in the non-XIP memory correspond to a same source image; an XIP memory for storing a shadowed boot loader code and OS images; a Central Processing Unit (CPU) for executing the OS images stored in the XIP memory; a code shadowing module for performing error detection checking on the OS images in the non-XIP memory and shadowing the boot loader code and OS images to the XIP memory; and a non-XIP interface for enabling the boot engine to access the non-XIP memory.

Growing community of inventors

Hsin-Chu, Taiwan

Ming-Shiang Lai