United Microelectronics Corp.

Ipenval Consultant Inc.

Personal Genomics, Inc.

Visera Technologies Company Limited

Voltafield Technology Corporation

Ming-Sheng Yang

Water Lur

Juan-Yuan Wu

Cheng-Yuan Tsai

Chih-Chien Liu

Hsueh-Chung Chen

Teng-Chun Tsai

Neng-Hui Yang

Hwi-Huang Chen

David Lee

Chao-Yuan Huang

Yueh-Feng Ho

Kuang-Chih Wang

Yung-Tsung Wei

Chin-Hsiang Lin

Chia-Lin Hsu

Yimin Huang

Teng-Chien Yu

Sheng-Fu Lin

Chia-Jui Chang

Chien-Min Lee

Tri-Rung Yew

Chin-Cheng Chien

Shih-Wei Sun

Wen-Yi Hsieh

Tong-Yu Chen

Chien-Hsin Lai

Jui-Tsen Huang

Kun-Chih Wang

Peng-Yih Peng

Anseime Chen

Keh-Ching Huang

Yi-Fang Cheng

Kuang-Ching Chen

Tsang-Jung Lin

Kuen-Jian Chen

Chia-Hung Kao

Chien-Mei Wang

Jia-Mou Lee

Tai-Lang Tang

Tzu-Guey Jung

Wen-Cheng Yeh

Ya-Yun Yu

Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive substrate; a light sensing region on the semiconductive substrate; a waveguide region configured to guide light from a wave insert portion through a waveguide portion and to a sample holding portion; and an interconnect region below the waveguide region, and the interconnect region being disposed above the light sensing region. The waveguide portion includes a first dielectric layer comprising a first refractive index and at least one second dielectric layer comprising a second refractive index, wherein the second refractive index is smaller than the first refractive index.

Optical sensor and manufacturing method thereof

Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive substrate. A light sensing region is on the semiconductive substrate. A waveguide region is configured to guide light from a wave insert portion through a waveguide portion and to a sample holding portion. The waveguide portion includes a first dielectric layer including a first refractive index. A second dielectric layer includes a second refractive index. The second refractive index is smaller than the first refractive index. A first interconnect portion is positioned in the waveguide portion, configured to transmit electrical signal from the light sensing region to an external circuit. The sample holding portion is over the light sensing region.

A testing assembly for testing a magnetic sensor comprises a testing interface and a detachable magnetic-field generator. The testing interface has a base plate and plurality of testing terminals. The base plate has a first side and a second side opposite to the first side. The plurality of testing terminals is arranged on the first side of the base plate. The detachable magnetic-field generator is arranged on the second side of the base plate in a detachable fashion. The detachable magnetic-field generator has a coil support and at least one coil winding around the coil support.

Testing assembly for testing magnetic sensor and method for testing magnetic sensor

An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.

Integrated circuit layout

A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure.

Semiconductor device

A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.

Stacked chip system

A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 &#x3bc;m and a depth of at least 5 &#x3bc;m. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value.

Method for fabricating a through-silicon via

A method for fabricating an image sensor device is disclosed. The method for fabricating an image sensor device comprises forming a photosensitive layer on a substrate. The photosensitive layer is exposed through a first photomask to form an exposed portion and an unexposed portion. The unexposed portion is partially exposed through a second photomask to form a trimmed part, wherein the second photomask comprise a first segment and a second segment that has a transmittance greater than that of the first segment. The trimmed part is removed to form photosensitive structures. The photosensitive structures are reflowed to form a first microlens and a second microlens having different heights.

Method for fabricating an image sensor device

An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringing fields between the lines. Multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels.

Air gap for dual damascene applications

An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Air gap formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device

An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Air gap for tungsten/aluminum plug applications

A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

Chemical mechanical polishing in forming semiconductor device

Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device

The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method includes providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etching mask. A second dielectric layer is formed between the conductor structures, which has a dielectric constant smaller than the first dielectric layer. The second dielectric layer also alternatively has air voids contained therein to reduce dielectric constant.

Method of forming interconnect structure with low dielectric constant

The present invention disclosed a method for manufacturing a semiconductor device on a semiconductor substrate, the method comprising the steps of: forming a gate dielectric layer on the semiconductor substrate. A gate is formed on the gate dielectric layer. A first ion implantation is performed to form extended source and drain shallow junctions in the semiconductor substrate. Spacer are formed on the side wall of the gate with liner between the gate and the spacers. The source and drain region is formed by performing a second ion implantation. A thermal annealing is used to eliminate the implantation defect and active the dopants. A surface treatment is used to form selective polycrystalline silicon on the gate and the source and drain region, thereby forming raised source and drain. A Cobalt layer is formed on the selective polycrystalline silicon. The Cobalt layer is reacted with the selective polycrystalline silicon on the gate and the raised source and drain region to form Cobalt silicide to eliminate the surface defect and lower sheet resistance of the source/drain regions.

Method of manufacturing a semiconductor device

Growing community of inventors

Hsinchu, Taiwan

Ming-Sheng Yang