Macronix International Co., Ltd.

Ming-Shang Chen

Tzung-Ting Han

Chun-Lien Su

Wenpin Lu

Wen-Pin Lu

Mam-Tsung Wang

Yin-Jen Chen

Ying-Che Lo

Kuan-Fu Chen

Meng-Hsuan Weng

Chun-Chi Wang

Baw-Chyuan Lin

Ming-Hung Chou

Chi-Yuan Chin

Uway Tseng

Hung-Yu Chiu

Chia-Shing Chen

Yih-Shi Lin

Yin Jen Chen

Chia-Wei Wu

Shaw-Hung Ku

Shih-Keng Cho

Tsung-Hsien Wu

Shih-Chin Lee

Tzung Ting Han

Kuan Fu Chen

Shih Chin Lee

Miao-Chih Hsu

Shang-Wei Lin

Kuei-Yun Chen

A non-volatile register is provided. The non-volatile register includes a plurality of cell strings with respect to a plurality of bit lines, wherein each cell string includes a plurality of cells. Each word line is respectively connecting to a gate of one cell for each cell string to correspondingly form a page. The pages are configured into: a central page used as a register to store registered data; and a plurality of dummy pages at both sides of the central page. The dummy pages are controlled to provide a boosted channel voltage to a portion of memory cells of the central page, not being programmed. A source selection transistor is connected to a first side for each cell string. A drain selection transistor is connected to a second side for each cell string.

Non-volatile register and implementation of non-volatile register

A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Diode-less array for one-time programmable memory

A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.

Non-volatile memory structure including stress material between stacked patterns

A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.

Methods for manufacturing memory and logic devices using the same process without the need for additional masks

Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.

Method of fabricating NAND-type flash EEPROMS without field oxide isolation

A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are provided over the substrate. The gate structures located underneath the word lines and isolated by the diffusion regions. Then, an etching stop layer is formed. The etching stop layer and the first dielectric layer have different etching selectivity. A second dielectric layer is formed over the substrate. Furthermore, a plurality of contact holes to the diffusion regions between the word lines are formed by using the etching stop layer as a self-aligned mask.

Method of forming a contact on a semiconductor device

Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.

Methods of trench and contact formation in memory cells

A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer, the tunneling dielectric layer and the substrate. Next, the mask layer is removed, so that the top surface of each isolation structure is higher than that of the first conductive layer. Next, a second conductive layer is formed on the exposed sidewalls of the isolation structures. Next, an inter-gate dielectric layer and a third conductive layer are sequentially formed on the substrate.

Method for manufacturing NAND flash memory

Method of fabricating NAND-type flash EEPROM without field oxide isolation

A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the substrate beside the stack gate structures. Then, a plurality of spacers is formed on the sidewalls of the stack gate structures. After that, a plurality of conductive pad layers is formed on the exposed doped regions. By forming the conductive pad layers, the resistance of the doped region in each memory cell can be reduced.

Non-volatile memory cell and fabricating method thereof and method of fabricating non-volatile memory

A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of word lines is formed on the stack gate strips and the dielectric strips. Thereafter, the stack gate strips exposed by the word lines are removed to form a plurality of openings. A plurality of spacers is formed on the sidewalls of the openings and the word lines. A dielectric layer is formed over the substrate. A plurality of contacts is formed in the dielectric layer and the dielectric strips between two adjacent word lines.

Non-volatile memory and fabricating method thereof

A method of forming a memory device having a self-aligned contact is described. The method includes providing a substrate having a floating gate dielectric layer formed thereon, forming a floating poly gate layer on the floating gate dielectric layer, forming a first silicon nitride layer on the floating poly gate layer, and forming a patterned photoresist layer on the first silicon nitride layer. The method further includes etching the first silicon nitride layer and the floating poly gate layer using the patterned photoresist layer as an etch mask, forming an oxide layer over the exposed etched areas, removing the patterned photoresist layer and the first silicon nitride layer to expose the floating poly gate layer, forming poly spaces in the floating poly gate layer, and depositing a second silicon nitride layer over the poly spaces of the floating poly gate layer to form a self-aligned contact.

Method of fabricating a memory device having a self-aligned contact

The present invention relates a method of controlling and monitoring the thickness variation of the film structure of a semiconductor wafer by monitoring the thickness variation of the film structure of a testing region. The method is characterized by etching the film structure of the testing region with a pattern density substantially compatible with that of the device region in order to precisely simulate the thickness variation of the film structure of a device region in a chemical mechanical polishing process.

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Hsinchu, Taiwan

Ming-Shang Chen