Spansion Llc.

Advanced Micro Devices Corporation

Cypress Semiconductor Corporation

Adesto Technologies Corporation

Hyundai Electronics America, Inc.

Ming Sang Kwan

Yi He

Zhizheng Liu

Shenqing Fang

Michael Allen Van Buskirk

Darlene G Hamilton

Youseok Suh

Xuguang Alan Wang

Sung-Yong Chung

Venkatesh P Gopinath

Nancy S Leong

Guowei Wang

Sung-Chul Lee

Yugi Mizuguchi

Mark W Randolph

Chi K Chang

David K Liu

Yuan Tang

Jein-Chen Young

Arthur Wang

Sheunghee Park

Sameer S Haddad

Wei Zheng

Jean Y Yang

Hsingya Arthur Wang

Meng Ding

John Dinh

Deepak Kamalanathan

Derric Lewis

John Ross Jameson

Jian Feng Chen

Peter Rabkin

Zhigang Wang

Richard M Fastow

Lee Edward Cleveland

Timothy J Thurgate

Yue-Song He

Shane Charles Hollmer

Ashot Melik-Martirosian

Jiang Li

Gulzar Ahmed Kathawala

Michael Van Buskirk

Sheung-Hee Park

Nathan Gonzales

Wing Leung

Haike Dong

Sungchul Lee

A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.

NAND memory cell string having a stacked select gate structure and process for forming same

NAND memory cell string having a stacked select gate structure and process for for forming same

A memory device can include at least one plate structure formed over a semiconductor substrate; an active region formed within the semiconductor substrate without lateral isolation structures; a plurality of bit line contact groups, each including bit line contacts to the active region disposed in a first direction; a plurality of storage contact groups, each including storage contacts to the active region disposed in the first direction; a plurality of gate structures, each including a main section extending in the first direction, and disposed between one bit line contact group and an adjacent storage contact group; and a two-terminal storage element disposed between each bit line contact and the at least one plate structure.

Programmable impedance memory device and related methods

In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) an access transistor having a drain coupled to a bit line, a source coupled to the programmable impedance element cathode, and a gate coupled to a word line; (iii) a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and (iv) a diode having a cathode at the second diffusion region, and an anode at the third diffusion region, where the diode is turned on during an erase operation on the programmable impedance element.

Resistive switching memory having a resistor, diode, and switch memory cell

A method of controlling a resistive switching memory cell can include: receiving a first command to be executed on the resistive switching memory cell; performing, in response to the first command, an erase operation to erase the resistive switching memory cell to an erased state; verifying the erased state of the resistive switching memory cell; performing a weak program operation to program the resistive switching memory cell to a first programmed state; and verifying the first programmed state of the resistive switching memory cell.

Dual program state cycling algorithms for resistive switching memory device

In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells arranged in a plurality of array blocks, where each resistive memory cell is configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction, and to be erased to a high resistance state by application of an erase voltage in a reverse bias direction; (ii) a plurality of anode plates corresponding to the plurality of array blocks, where each resistive memory cell can include a resistive storage element having an anode coupled to one of the anode plates; (iii) an inactive ring surrounding the plurality of anode plates, where the inactive ring can include a same material as each of the plurality of anode plates; and (iv) a plurality of boundary cells located under the inactive ring.

Resistive switching memory device architecture for reduced cell damage during processing

In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.

Capacitor arrangements using a resistive switching memory cell structure

A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Controlling AC disturbance while programming

A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Strapping contact for charge protection

Growing community of inventors

San Leandro, CA, United States of America

Ming Sang Kwan