University of Electronic Science and Technology of China

Institute of Electronic and Information Engineering of Uestc in Guangdong

Ming Qiao

Bo Zhang

Zhengkang Wang

Ruidi Wang

Zhaoji Li

Zhao Qi

Wentong Zhang

Longfei Liang

Nailong He

Yibing Wang

Wenliang Liu

Dong Fang

Chunlan Lai

Linrong He

Yi Bu Li

Xi Hu

Yang Yu

Zhao Wang

Yong Chen

Sen Zhang

Teng Liu

Dican Hou

Zhangyi'an Yuan

Shuhao Zhang

Ning Tang

Yilei Lyu

Wenyang Bai

Fabei Zhang

Song Pu

Liu Yuan

Shida Dong

Dingxiang Ma

Jun Ye

Bo Luo

Jiamu Xiao

Zhenya Zhan

Danye Liang

Li Ye

A new variable selective etching technology for thick SOI devices. An SOI material is etched by the following steps: (1) providing an SOI wafer; (2) depositing a composite hard mask with a variable selection ratio to replace a traditional hard mask with an invariable selection ratio; (3) applying a photoresist; (4) mask making, namely defining a to-be-etched region by using a photoetching plate; (5) etching the photoresist in the defined region; (6) etching the composite hard mask; (7) removing the photoresist; (8) etching top silicon by using a second etching method at a first selection ratio; and (9) etching a buried oxide layer by using a third etching method at a second selection ratio. The new variable selective etching technology avoids the damage to a side wall of a deep trench when the buried oxide layer is etched, and does not need to use an excessive thick hard mask.

Variable selective etching technology for thick SOI devices

A termination structure of a super-junction power device has a novel polysilicon resistive field plate at the top of a termination region between a transition region and an edge of the device. By utilizing the regular distribution of potential in the field plate, an additional electric field is introduced at the top of the termination structure to limit the expansion of a non-depletion region and optimize the distribution of charges. The termination structure includes a first doping type epitaxial layer, a second doping type compensation region, a second doping type body region, a second doping type lateral connection layer, a second doping type body contact region, a first doping type source contact region, a gate oxide layer, a passivation layer, a field oxide layer, a gate electrode, a second doping type edge contact region, a polysilicon resistive field plate, a metal layer and the like.

Termination structure of super-junction power device comprising plurality of runway-shaped rings as the resistive field plate

A method for manufacturing a semiconductor device is provided. A drift region and a compensation region are formed through a deep trench etching and a filling technology. A plurality of modulation doping regions are formed at a top of the drift region by an epitaxy and an ion implantation. A modulation region is introduced, wherein the modulation region flexibly modifies capacitance characteristics and achieve improved dynamic characteristics.

Semiconductor device and manufacturing method

A bidirectional conduction trench gate power MOS device and a manufacturing method thereof are provided. A gate electrode, a source electrode and a drain electrode are formed on a surface of a silicon wafer to realize a bidirectional conduction and bidirectional blocking power MOS device used in an application environment such as lithium battery BMS protection. A device structure of the bidirectional conduction trench gate power MOS device has advantages compared with double-transistor series connection used in a conventional BMS and other structures for realizing a bidirectional conduction: firstly, the bidirectional conduction trench gate power MOS device needs to occupy half or less area compared with a conventional mode, improving a degree of integration; secondly, the device structure has a simple manufacturing process and a low manufacturing cost reducing manufacturing problems; thirdly, the drain electrode and the source electrode of the device structure are exchanged to realize a symmetrical structure.

Bidirectional conduction trench gate power MOS device and manufacturing method thereof

A lateral power semiconductor device includes a first type doping substrate at a bottom of the lateral power semiconductor device, a second type doping drift region, a second type heavy doping drain, a first type doping body; a first type heavy doping body contact and a second type heavy doping source, where dielectric layers are on a right side of the second type heavy doping source; the dielectric layers are arranged at intervals in a longitudinal direction in the first type doping body, and between adjacent dielectric layers in the longitudinal direction is the first type doping body; and a polysilicon is surrounded by the dielectric layer at least on a right side. Compared with conventional trench devices, the lateral power semiconductor device introduces a lateral channel, to increase a current density, thereby realizing a smaller channel on-resistance.

Lateral power semiconductor device

An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.

SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof

A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cof the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Ccaused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.

Power semiconductor device

A power semiconductor device for improving a hot carrier injection is provided. A drain field plate is introduced at one side of a drain in a dielectric trench and connected to a drain electrode, having identical electric potential, thereby improving hole injection effects at a drain side of the dielectric trench. A shield gate field plate is introduced at one side of a source electrode in the dielectric trench and is connected to the source electrode or ground, thereby forming a shield gate. While decreasing gate drain parasitic capacitance C, electron injection effects at a source electrode side of the dielectric trench are improved. With a trench etching method, the improvement of hot carrier injection can also be achieved by making carriers avoid a side wall of the dielectric trench on a path.

Power semiconductor device for improving hot carrier injection

A low specific on-resistance (R) power semiconductor device includes a power device and a transient voltage suppressor (TVS); wherein the power device comprises a gate electrode, a drain electrode, a bulk electrode, a source electrode and a parasitic body diode, the bulk electrode and the source electrode are shorted, the TVS comprises an anode electrode and a cathode electrode, the drain electrode of the power device and the anode electrode of the TVS are connected by a first metal to form a high-voltage terminal electrode, the source electrode of the power device and the cathode electrode of the TVS are connected by a second metal to form a low-voltage terminal electrode.

Power semiconductor devices with low specific on-resistance

An integrated power semiconductor device, includes devices integrated on a single chip. The devices include a vertical high voltage device, a first high voltage pLDMOS device, a high voltage nLDMOS device, a second high voltage pLDMOS device, a low voltage NMOS device, a low voltage PMOS device, a low voltage NPN device, and a low voltage diode device. A dielectric isolation is applied to the first high voltage pLDMOS device, the high voltage nLDMOS device, the second high voltage pLDMOS device, the low voltage NMOS device, the low voltage PMOS device, the low voltage NPN device, and the low voltage diode device. A multi-channel design is applied to the first high voltage pLDMOS device, and the high voltage nLDMOS device. A single channel design is applied to the second high voltage pLDMOS device.

Integrated power semiconductor device and method for manufacturing the same

A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.

Power MOS device with low gate charge and a method for manufacturing the same

The present invention provides a high voltage ESD protection device including a P-type substrate; a first NWELL region located on the left of the upper part of the P-type substrate; an NP contact region located on the upper part of the first NWELL region; an N+ contact region located on the right of the upper part of the P-type substrate apart from the first NWELL region; a P+ contact region tangential to the right side of the N+ contact region; a NTOP layer arranged on the right of the NP contact region inside the first NWELL region. The NP contact region is connected to a metal piece to form a metal anode. The N+ contact region and the P+ contact region are connected by a metal piece to form a metal cathode.

High voltage ESD protection device

A split-gate enhanced power MOS device includes a substrate and an epitaxial layer formed on an upper surface of the substrate. A control gate trench is provided in the epitaxial layer. The control gate trench includes a gate electrode and a split-gate electrode. The gate electrode includes a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode are located in an upper half portion of the control gate trench and are separated by a first dielectric layer. The first gate electrode and the second gate electrode are located above the split-gate electrode and are separated from the split-gate electrode by a second dielectric layer. The first gate electrode and the second gate electrode are separated from a body region in the epitaxial layer by a gate dielectric.

Split-gate enhanced power MOS device

A BIPOLAR-CMOS-DMOS (BCD) semiconductor device and manufacturing method, which can integrate a Junction Field-Effect Transistor (JFET), two classes of Vertical Double-diffusion Metal Oxide Semiconductor (VDMOS), a Lateral Insulated-Gate Bipolar Transistor (LIGBT) and seven kinds of Laterally Diffused Metal Oxide Semiconductor (LDMOS), a low-voltage Negative channel Metal Oxide Semiconductor (NMOS), a low-voltage Positive channel Metal Oxide Semiconductor (PMOS), a low-voltage Negative-Positive-Negative (NPN) transistor and a low-voltage Positive-Negative-Positive (PNP) transistor, and a diode in the same chip. Bipolar devices in the analog circuit, power components in the switch circuit, Complementary Metal Oxide Semiconductor (CMOS) devices in the logic circuit and other kinds of lateral and vertical components are integrated. This present invention saves costs at the same time greatly improve chip integration. The manufacturing method of the present invention is simple, and the difficulty of process is relatively less.

Bipolar-CMOS-DMOS semiconductor device and manufacturing method

A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 &#x3bc;m, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region.

Growing community of inventors

Chengdu, China

Ming Qiao