Industrial Technology Research Institute

Ming-Mao Chiang

Ming-Fen Lin

Ruen-rone Lee

Won-Yih Lin

Ming-Tsan Kao

An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f,<f,<f,or 0.5f,<f,<f,, where f,is the write frequency if f,is the read frequency, or vice versa. A FIFO in accordance with the present invention comprises a dual port random access memory, a read pointer, a write pointer, a synchronization circuit and a status indicator. In the FIFO design, the read pointer indicating the read address is a simple sequential counter, and the write pointer indicating the write address is a Gray code counter. Gray code to sequential count converters are used to convert the Gray codes to sequential counts. The synchronization circuit synchronizes the write pointer and the read pointer using a read clock. A status indicator with simple circuits is provided to indicate if the FIFO is almost full or empty.

Apparatus and method for asynchronous dual port FIFO

Disclosed is an improved computer graphics memory architecture. The architecture includes an address translation table (ATT) and a buffer. The address translation table receives information about desired pixel data and determines the physical address of the desired data. The buffer is connected to the ATT and has a dual bank which stores the color value and the Z value of a 3-D pixel. A buffer addressing method is also provided in which the address of the desired pixel information and associated control circuits may be quickly determined through an appropriate data arrangement in the buffer and an address transfer table.

Growing community of inventors

Hsinchu, Taiwan

Ming-Mao Chiang