Advanced Micro Devices Corporation

Marvell International Limited

Samsung Electronics Co., Ltd.

Qualcomm Incorporated

Alibaba Group Holding Limited

Ming Lin

Minh Van Ngo

Qi Xiang

Haihong Wang

Li Feng Zhang

Paul Raymond Besser

James N Pan

Yungping Hsu

Vikas Sinha

Alessandro Risso

Tsunglun Yu

Zvi Guz

Afshin Haftbaradaran

Shravan Kumar Reddy Garlapati

Sek Kin Neng

Naveen-Kumar Arani

Shu Li

Songping Wu

Eric N Paton

Mao Yu

Jung-Suk Goo

Subramanya P Rao

Quan Zhou

Sergey Timofeev

Alexandre Pierrot

Cunzhen Liu

Harsha Narasimha Acharya

A system and method for leveraging a native operating system page cache when using non-block system storage devices is disclosed. A computer may include a processor, memory, and a non-block system storage device. A file system may be stored in memory and running on the processor, which may include a page cache. A key-value file system (KVFS) may reside between the file system and the storage device and may map received file system commands to key-value system commands that may be executed by the storage device. Results of the key-value system commands may be returned to the file system, permitting the operating system to cache data in the page cache.

System and methods for providing fast cacheable access to a key-value device through a filesystem interface

Methods, systems, and devices for wireless communications are described. A shared channel may include a set of tones carrying multiple types of control information multiplexed together. A wireless device may perform a tone classification method to determine individual subsets of tones from the set of tones for each type of control information to extract each type of control information. The wireless device may determine multiple subsets of tones correspond to multiple types of control information simultaneously based on different extraction parameters. For example, the wireless device may determine a total number of tones in a set of tones, a distance between any given two tones in the set of tones, an offset value, or any combination thereof for the extraction parameters. The wireless device may then use these extraction parameters to determine or extract two or more subsets of tones for two or more corresponding types of control information.

Tone classification for physical channels with multiplexed data

A system and method for leveraging a native operating system () page cache () when using non-block system storage devices () is disclosed. A computer () may include a processor (), memory (), and a non-block system storage device (). A file system () may be stored in memory () and running on the processor (), which may include a page cache (). A key-value file system (KVFS) () may reside between the file system () and the storage device () and may map received file system commands () to key-value system commands () that may be executed by the storage device (). Results of the key-value system commands () may be returned to the file system (), permitting the operating system () to cache data in the page cache ().

Methods, systems, and devices for wireless communications are described. In some systems, a first device may transmit a signal to a second device including a number of error detection bits interleaved with a number of information bits. The second device may use the error detection bits to determine if the signal was received correctly, where each error detection bit may be associated with a set of information bits. The second device may progressively decode the signal and continuously perform an error detection calculation based on a first set of information bits associated with a first error detection bit. Based on the error detection calculation, the second device may calculate an expected error detection bit corresponding to the first error detection bit. The second device may compare the first error detection bit to the expected error detection bit. Other aspects and features are also claimed and described.

Error detection for a wireless channel

Embodiments described herein provide a system for facilitating a lightweight distributed storage system. During operation, the system generates a data segment from a data file associated with a write operation and determines a storage key for the data segment. The storage key indicates a calculated storage path associated with a replica of the data segment. The system then determines whether a user-defined storage path is specified by a user for the data segment. If a user-defined storage path has not been specified by the user for the data segment, the system generates a data packet comprising the data segment, wherein a destination for the data packet corresponds to a target disk specified by the calculated storage path.

Low-latency lightweight distributed storage system

Systems, methods, and other embodiments associated with unified control of timing recovery and packet processing are described. According to one embodiment, a method for performing unified control of timing recovery and packet processing is provided. The method includes sampling a received signal according to an ADC timing signal to produce a sequence of samples. The received signal corresponds to a packet and was transmitted according to a transmit timing signal. The method includes determining a phase offset between the ADC timing signal and the transmit timing signal and identifying, based, at least in part, on the phase offset, a data portion of the sequence of samples that contains data encoded in the received signal. A re-generated sample sequence that adjusts the data portion based on the phase offset is calculated.

Unified control for digital timing recovery and packet processing

Systems and techniques relating to wireless communications are described. A described technique includes receiving a signal via a wireless channel, performing code synchronization by at least using a peak counter to count peak correlations based on the signal and a known preamble, performing frequency synchronization based on the signal, and using, based on a successful completion of the code synchronization, at least a result of the frequency synchronization to demodulate data from the signal. The technique includes starting the frequency synchronization during the code synchronization when an output value of the peak counter satisfies a predetermined criterion.

Parallel processing of both code synchronization and frequency synchronization for wireless communication

A receiver is provided and includes a first amplifier configured to amplify, based on a first gain, a radio frequency signal to generate a first amplified signal. The radio frequency signal is received by the receiver on a first channel. A second amplifier generates, based on the first amplified signal and a second gain, a second amplified signal. An output circuit generates a baseband signal based on the second amplified signal. A first detection circuit compares the baseband signal to (i) a first threshold in response to the first gain being at a first level, and (ii) a second threshold in response to the first gain being at a second level. The first detection circuit generates a first detection signal in response to the comparison. A controller, in response to the first detection signal, (i) adjusts the second gain, or (ii) changes the receiver from the first channel.

Apparatus and methods for detection of interface in radio-frequency devices

A communication apparatus includes a radio frequency (RF) apparatus. The RF apparatus includes an amplifier, and a signal detection circuit. The amplifier receives RF signals and amplifies those signals. The amplifier has an adjustable gain value. The signal detection circuit detects whether a received signal is an out-of-band radar signal depending on the gain value of the amplifier and a characteristic of the received signal.

An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Tensile strained substrate

Semiconductor with tensile strained substrate and method of making the same

Strained silicon is grown on a dielectric material in a trench in a silicon germanium layer at a channel region of a MOSFET after fabrication of other MOSFET elements using a removable dummy gate process to form an SOI MOSFET. The MOSFET is fabricated with the dummy gate in place, the dummy gate is removed, and a trench is formed in the channel region. Dielectric material is grown in the trench, and strained silicon is then grown from the silicon germanium trench sidewalls to form a strained silicon layer that extends across the dielectric material. The silicon germanium sidewalls impart strain to the strained silicon, and the presence of the dielectric material allows the strained silicon to be grown as a thin fully depleted layer. A replacement gate is then formed by damascene processing.

Semiconductor on insulator MOSFET having strained silicon channel

The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.

Strained silicon MOSFET having reduced leakage and method of its formation

The formation of shallow trench isolations in a strained silicon MOSFET includes implantation of a dopant into overhang portions of the strained silicon layer and silicon germanium layer at the edges of trenches in which shallow trench isolations are to be formed. The conductivity type of the dopant is chosen to be opposite the conductivity type of the source and drain dopants. The implanted dopant increases the threshold voltage Vt beneath the ends of the gate in overhang portions of the strained silicon layer so that it is approximately equal to or greater than that of the remainder of the MOSFET. The resulting strained silicon MOSFET exhibits reduced leakage current beneath the ends of the gate.

Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends

A method of manufacturing an integrated circuit with a strained semiconductor channel region. The method can provide a double gate structure. The gate structure can be provided in and above a trench. The trench can be formed in a compound semiconductor material such as a silicon-germanium material. The strained semiconductor can increase the charge mobility associated with the transistor. A silicon-on-insulator substrate can be used.

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San Jose, CA, United States of America

Ming Lin