Macronix International Co., Ltd.

Ming-Liang Wei

Po-Kai Hsu

Hang-Ting Lue

Teng-Hao Yeh

Yu-Hsuan Lin

Ming-Hsiu Lee

Hsiang-Pang Li

Dai-Ying Lee

Yun-Yuan Wang

Chia-Lin Yang

Cheng-Hsien Lu

Bo-Rong Lin

Chao-Hung Wang

Hsiang-Yun Cheng

Zu-Heng Liu

Nai-Jia Dong

A memory device and a computing method thereof are provided in the present disclosure. The computing method includes the following steps. A plurality of input-values of a model computation are respectively received through a plurality of first-word-lines of a memory array. Inverted logic values of the input-values are respectively received through a plurality of second-word-lines. The input-values are respectively received through a plurality of first-bit-lines. The inverted logic values are respectively received through a plurality of second-bit-lines. Logic XNOR operation is performed according to each of the input-values and each of the inverted values to obtain a first computation result, and multiplied with one of self-coefficients or one of mutual coefficients of the model computation to obtain a plurality of output-values. The output-values are outputted through a plurality of common-source-lines.

Memory device and computing method thereof

The present invention discloses a memory and a training method for neural network based on memory. The training method includes: obtaining one or more transfer functions of a memory corresponding to one or more influence factors; determining a training plan according to an ideal case and the one or more influence factors; training the neural network according to the training plan and the one or more transfer functions to obtain a plurality of weights of the trained neural network; and programming the memory according to the weights.

Memory and training method for neural network based on memory

Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.

Memory device and operation method thereof

A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

Memory system for maintaining data consistency and operation method thereof

An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.

In-memory multiply-add computing device adapted to process input signals with improved accuracy

A memory apparatus and compensation method for a computation result thereof are provided. The memory apparatus includes a memory sub-block, a reference memory sub-block and a control circuit. During a computation phase, the memory sub-block receives an input signal, and generates a computation result by a multiply-accumulate operation according to the input signal. The reference memory sub-block includes a plurality of memory cells pre-programmed with a reference weight value. The reference memory sub-block receives a reference input signal during a calibration phase, and generates a reference computation value by a multiply-accumulate operation according to the reference input signal and the reference weight value. The control circuit generates an adjustment value according to the reference computation value and a standard computation value, and during the computation phase, adjusts the computation result according to the adjustment value to generate an adjusted computation result.

Memory apparatus and compensation method for computation result thereof

A data sensing device and a data sensing method are provided. The data sensing device includes a current adjuster and a sensing amplifier. The current adjuster corresponds to a memory string of a memory array, generates a shift current according to an amount of a plurality of input signals of the memory string, and generates an adjusted read-out current by adjusting a read-out current of the memory string according to the shift current. The sensing amplifier receives the adjusted read-out current and a plurality of reference currents, and generates a read-out data by comparing the adjusted read-out current and the plurality of reference currents.

Data sensing device and data sensing method thereof

A memory storage device includes: a memory array for generating a cell current dependent to an input and transconductance of memory cells of the memory array; a reference array for generating a reference current; an ADC for performing analog-digital-conversion on the cell current based on the reference current to generate a digital output; and a memory controller for generating an output based on the input and the digital output of the ADC. The output of the memory controller indicates an inner product of the input and a weight, the weight including a positive weight and a negative weight. The positive weight is implemented by the transconductance of the memory cells of the memory array. The negative weight is implemented by transconductance of reference cells of the reference array or implemented by a shifting number of a shifter in the memory controller.

Memory storage device and operation method thereof for implementing inner product operation

A data sensing device and a data sensing method thereof are provided. The data sensing device includes a compensation signal generator, a weighting operator and an arithmetic operator. The compensation signal generator receives a basic input signal and a plurality of reference weighting values, and generates a compensation signal according to the basic input signal and the reference weighting values. The weighting operator has a plurality of memory cells, performs a writing operation on the memory cells according to the weighting values based on address information, and the weighting operator generates an output signal by the memory cells by receiving a plurality of input signals. The arithmetic operator performs an operation on the output signal and the compensation signal to generate a compensated output signal.

Growing community of inventors

Kaohsiung, Taiwan

Ming-Liang Wei