Advanced Micro Devices Corporation

Ati Technologies Ulc

Ming L So

Alexander J Branover

Xiaojie He

Xiao Gang Zheng

Maurice B Steinman

Mihir Shaileshbhai Doctor

Arvind Bomdica

Kevin Yikai Liang

Biao Zhou

Fei Fei

Evgeny Mintz

Felix Yat-Sum Ho

Philip Ng

Benjamin Tsien

Grigori Temkine

Oleg Drapkin

Carl Kittredge Wakeland

Min Xu

Paul Blinzer

Andrew William Lueck

Christopher T Weaver

Walter G Fry

Francisco Leonel Duran

Ali Ibrahim

Gary H Simpson

Krishna Sai Bernucho

Mom-Eng Ng

Siji Menokki Kandiyil

Samu Suryanarayana

Marcus Ng

Kenny Xu

Scott E Matlock

Xiaogang Zheng

Dan P Shimizu

Laura M Smith

Felix Ho

Joseph Scanlon

A computer processing device transitions among a plurality of power management states and at least one power management sub-state. From a first state, it is determined whether an entry condition for a third state is satisfied. If the entry condition for the third state is satisfied, the third state is entered. If the entry condition for the third state is not satisfied, it is determined whether an entry condition for the first sub-state is satisfied. If the entry condition for the first sub-state is determined to be satisfied, the first sub-state is entered, a first sub-state residency timer is started, and after expiry of the first sub-state residency timer, the first sub-state is exited, the first state is re-entered, and it is re-determined whether the entry condition for the third state is satisfied.

Power state transitions

Multi-tiered low power states

Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.

Aligning active and idle phases in a mixed workload computing platform

Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus.

Emulated legacy bus operation over a bit-serial bus

A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.

Method and apparatus for transitioning a system to an active disconnect state

A circuit for use in a computing system including a bus interface unit and an autoload controller. The autoload controller has an input to receive an initialization signal. In response to receiving the initialization signal, the autoload controller searches for a signature using the bus interface unit and, in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the address, and provides the plurality of base addresses to a control output thereof.

Circuit and method for initializing a computer system

An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

Method and apparatus for controlling a communication signal by monitoring one or more voltage sources

A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.

North-bridge to south-bridge protocol for placing processor in low power state

Embodiments of a method and system for conserving power used in a central processing unit (CPU) are described. An embodiment uses direct memory access (DMA) fetch suspend logic to allow the CPU to stay in a sleep state indefinitely until a break event occurs. Embodiments include power management monitoring and Universal Serial Bus (USB) descriptor monitoring logic. Power management monitor logic monitors the CPU sleep state and sets a status flag to the USB descriptor monitoring logic whenever the CPU is in a predefined sleep state. The USB descriptor monitoring logic monitors the fetching of linked descriptor lists. When the CPU status flag is raised, it causes monitoring of the descriptor fetch by the USB descriptor monitoring logic. If the USB controller has completed all of the descriptor fetches while the CPU sleep flag is true, this logic sets a flag to cause the USB controller to suspend DMA fetch operations.

USB power conservation method and apparatus

An ultra-low power crystal oscillator architecture that draws less than 2 &#x3bc;A during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 &#x3bc;A.

Ultra-low power crystal oscillator

Growing community of inventors

Danville, CA, United States of America

Ming L So