Mosel Vitelic Corporation

Ming-Kuan Kao

Jui-Ping Li

Ping-Wei Lin

Yi-Shin Chang

Chien-Hung Chen

Chien-Hung Zordius Chen

Wei-Shang King

Yi-Fu Chung

Jason C S Chu

Jui-ping Li

Ping-wei Lin

Yi-Fu Chang

Hui-ching Lin

A method of fabricating an oxide/nitride multilayer structure is disclosed. The multilayer structure of dielectric films could be applied for manufacturing E PROM, flash memories, or the dielectric layers of a DRAM capacitor. In accordance with the present invention, all films are formed in the same chamber, and only one heating and one cooling step are needed to form an oxide/nitride/oxide structure or an oxide/nitride/oxide/nitride structure.

Method of fabricating an oxide/nitride multilayer structure for IC manufacture

A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator

A method for measuring the parameter of a rough film is presented in this invention. In which the optical property of a rough film is further defined by utilizing the characteristics of an optical instrument and silicon film, without disturbance from noise in measurement. Therefore, good or bad the rough film is can be detected effectively, further, a handy method can be offered to control the stability in the manufacturing process. The invention is performed by choosing a measuring light with wavelength in a certain range and an optical instrument, then comparing the result with a standard value to monitor the result of the manufacturing process of the rough film.

Method for measuring the parameter of a rough film

An irradiation process method for forming polysilicon layer is disclosed. The method includes firstly forming an alpha-silicon layer on substrate. Then the temperature of the UHV-CVD chamber is increased and the wafer is sent into the chamber. Gas is then intermittently conducted into the vacuum-chamber apparatus. While increasing the temperature of the vacuum-chamber apparatus, the whole throughput thus increases and the process-time for the polysilicon layer thus decreases. Finally, the electrical capacity thus increases by forming the polysilicon layer.

Method for forming a hemispherical-grain polysilicon

A method for improving trench isolation is disclosed. A trench is etched into the substrate by using a photo mask. A bottom oxide layer, a sidewall oxide layer and a polycrystalline silicon layer are deposited into the trench and over the wafer, and are etched to clear from the surface, then over-etched till a recess is formed within the trench. Thereafter, an oxide etch step is applied to remove a certain thickness of the sidewall oxide layer in order to expose the polycrystalline silicon edge in the opening of the trench. Then, an oxidation step is utilized to form a capping oxide layer on top of the recess by oxidizing the top and the exposed edge of the polycrystalline silicon film in the trench so that a uniform plug edge can be achieved inside the trench to prevent stress problem induced by a wedge shaped oxide growing in the space between the plug and the substrate.

Method for improving trench isolation

A method of forming a field oxide isolation region includes: forming a first pad oxide layer over a semiconductor substrate; forming a silicon nitride layer over the first pad oxide layer; patterning and etching the silicon nitride layer and the first pad oxide layer to expose a portion of the substrate, and simultaneously forming an undercut cavity; forming a second pad oxide layer over the exposed portion of the substrate; depositing a layer of polysilicon over the second pad oxide layer, the polysilicon layer filling the undercut cavity to form a polysilicon plug; removing portions of the polysilicon layer to form a polysilicon spacer; thermally oxidizing the substrate to substantially consume the polysilicon spacer but leave a polysilicon residual of the polysilicon plug, the thermal oxidation forming a thick oxide above the exposed portion of the substrate; substantially removing the silicon nitride layer; applying a first etching solution to the first pad oxide layer and the polysilicon residual, the first etching solution providing selective etching of the first pad oxide layer and the polysilicon residual so that the polysilicon residual is substantially removed and the first pad oxide layer is partially removed leaving a first pad oxide layer residual; and applying a second etching solution to remove the first pad oxide layer residual, thereby leaving the thick oxide to form the isolation region.

Method of removing polysilicon residual in a LOCOS isolation process using an etching selectivity solution

The present invention relates to a method for forming rugged polysilicon capacitance electrodes uses for dynamic random access memory processes is disclosed. The method is capable in reducing process time, enhancing yield, and saving production cost. Wherein, the process of the present invention comprises: firstly, a semiconductor wafer is delivered into a low pressure chemical vapor deposition (LPCVD) tube. Herein, a non-doped or doped amorphous silicon layer is deposited on the surface top of electrodes. A rugged polysilicon capacitance is formed on top of the non-doped or doped amorphous silicon layer by using the methods of rising temperature and decreasing pressure. Then, an ion implantation is applied and follows by a wafer cleaning procedure and an annealing process, wherein those procedures are accomplished after the removal of the wafer from LPCVD tube. During the annealing process, the non-doped or doped amorphous silicon layer is transformed into a polysilicon layer under a temperature roughly about 850.degree.C. In particularly, an in-situ phosphorous doped amorphous silicon can be deposited prior to the formation of non-doped amorphous silicon layer, and won't influence the stages that follow.

Method for forming rugged polysilicon capacitor

Method to prevent the formation of a thinner portion of insulating layer

The present invention provides a method for enlarging the surface area of hemi-spherical grains on the surface of a semiconductor chip. The hemi-spherical grain structure is formed by combining a poly-silicon layer with an underlying amorphous silicon layer. In processing, the two layers are etched with a corrosive solution that etches the amorphous silicon layer at a higher rate than it etches the poly-silicon layer. In this way, a ring-shaped slot forms at the bottom of each hemi-spherical grain thus increasing the total surface area of the hemi-spherical grain structure. Furthermore, surface area of the storage node is increased and the cell capacitor capacitance increases in excess of 15%.

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Hsinchu, Taiwan

Ming-Kuan Kao