Integrated Telecom Express, Inc.

Realtek Semiconductor Inc.

Pctel, Inc.

Real Communications, Inc.

Other

Ming-Kang Liu

Steve S Chen

Young Way Liu

Chiihsin Kao

Chunta Chen

Whu-Ming Young

Victor S Lee

Wen Chi Chen

John N Gross

Ta-Yung Lee

Man Ho Ku

Chin-I Huang

Meng-Chieh Tsao

Yukuang Wang

Zhouhui Miao

Dean C Wang

Wen-Ching Andy Chou

A method of implementing a scaleable architecture for a communications system considers the requirements of a particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs achievable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field. A system constructed in this fashion is highly gate efficient and cost effective, so that a multiport system can be put on single SOC integrated circuit.

Mixed hardware/software architecture and method for processing communications

A task scheduler for a TC subsystem is disclosed. The task scheduler is responsible for responding to computation block requests from the TC subsystem, and retrieving/storing data objects for such computation blocks. The task scheduler thus facilitates a type of logical pipeline by exchanging such data objects with a common TC memory used by each computation block. The task scheduler generally includes a queue, a state machine and a bus master for satisfying the data object requests.

Programmable task scheduler

A data communication device with a receiver for receiving and processing incoming signal having intersymbol interference component to produce resultant signals with less interference. The processor includes a timing recovery processor for recovering a clock signal from the sample streams of the incoming signal. The recovered clock signal is also suitable for signal detection of the incoming signals under strong intersymbol interference.

Optimum phase timing recovery in the presence of strong intersymbol interference

An improved type of application-specific integrated circuit block (ASIC) is disclosed that is optimized for use in a communications system, and is somewhat programmble through the use of particular data objects that can specify an instruction and operand for the ASIC. The ASIC can be multi-tasking to perform multiple receive or transmit operations, two different kinds of transmit or receive operations, and operaions for mulitple ports. The ASIC generally uses an input data decoder block for decoding an input data object; a computation logic block for performing application specific computations in connection with the input data object, and an output data encoder block for encoding an output data object based on the specific computations. Using a common memory, a set of such ASICs can be arranged in a form of logical (or logical hybrid) pipeline.

xDSL function ASIC processor and method of operation

A physical medium dependent (PMD) transport subsystem is disclosed which is used in an xDSL communication system. The PMD subsystem coordinates movement of data from an analog front end to a logical pipeline based TC layer, and exchanges common data objects with the latter to increase flexibility of the system. The PMD subsystem includes a number of ASIC blocks for performing signal processing operations, and these ASIC blocks are also shared between ports and are multi-tasking to reduce hardware costs.

Physical medium dependent sub-system with shared resources for multiport xDSL system

A communications system including a shared signal circuit for performing a set of signal processing operations on both receive data and transmit data. The signal processing circuit is also shared by a plurality of communication ports. To further enhance operation of the system, the computing resources include a set of independent application specific (ASIC) logic circuits, with at least some of the ASICs selectively performing at least one of a first signal processing operation and a second signal processing operation on data in response to control information embedded in an input data object.

xDSL communications systems using shared/multi-function task blocks

A multi-port communications system is described, which includes hardware based subsystems for performing both physical medium dependent operations and transport convergence operations on a data transmission. A software based subsystem performs other operations as needed. Both types of subsystems are shareable by the communications ports so as to reduce a total hardware requirement of a communications system. In addition, processing blocks within both subsystems are adapted to be multi-tasking, in that they can perform multiple operations for a receive/transmit task, or even a mixture of receive/transmit tasks. The subsystems are arrangeable in a logical/hybrid pipeline arrangement with a common memory to further maximize the flexibilty and configurability of a communications system.

Scaleable architecture for multiple-port, system-on-chip ADSL communications systems

A system that can be dynamically configured to achieve an optimal routing path for an end-to-end data link connection is disclosed. An optimal data path can be determined by a digital subscriber loop (DSL) user based on particular bandwidth requirements, data rate cost constraints, and/or data delay requirements. The data path can be set up to include one or more data routes, including the regular digital public switching telephone network (PSTN), a wide area networks (WAN), or virtual permanent circuit links via digital cross-connects (DCS).

Configurable digital subscriber loop access and end-to-end data and analog voice connection system

A transport convergence (TC) subsystem for use as a form of logical pipeline processor is disclosed. The TC subsystem includes a number of ASIC computing blocks interconnected through a local bus for transferring data objects used as a form of common data I/O for each ASIC. The data object includes both control and data portions. A TC scheduling circuit coordinates transfer of data objecst to and from a TC data object memory that is local or external. The TC data object memory is shared in common with all the ASIC blocks so that computation results from each ASIC TC signal processing circuit can be passed between other ASICs to form a logical pipeline. The data objects output from the TC subsystem are used by other processing subsystems in an xDSL communications system, including a software based ATM TC subsystem, and a physical medium dependent subsystem. In addition, the architecture of the TC subsystem is configured so that it can be shared by multiple ports in an xDSL system. The individual ASICs are also adapted to be multi-tasking to further reduce hardware requirements.

Transport convergence sub-system with shared resources for multiport xDSL system

A structure for a data object is disclosed with a field and format structure optimized for use by a set of pipeline stages that are interconnected logically through a common pipeline memory. The data object includes both a first portion containing data relating to one or more of a plurality of parameters associated with the control and/or the configuration of one or more processing circuitry blocks, and a second portion containing data associated with computations performed by the processing circuitry blocks. Other portions contain both general and specific types of operational control information used by the processing circuitry blocks. The data object acts as a form of common data exchange mechanism between disparate types of pipeline stages, including in hybrid (mixed) software-hardware pipelines. The control data in the data object can be used by a first pipeline stage to affect or adaptively change operational functioning of downstream pipeline stages.

Data object architecture and method for xDSL ASIC processor

A communications system operates with an internal pipeline clock rate that is higher than that of any port used in the system. In an xDSL environment, this rate is higher than a DMT symbol rate used in the channel. In this manner, communications for the various ports can be synchronized and pipelined for transmit/receive operations. In addition, the higher rate results in idle processing periods, during which stuffing symbols are generate to maintain synchronism and/or pass along control information. The internal pipeline clock rate is selected to be higher than rate that may be encountered as well during an initialization routine and normal transmissions. The pipeline clock is also programmable so as to permit power management of the system.

System and method for a family of digital subscriber line (XDSL) signal processing circuit operating with an internal clock rate that is higher than all communications ports operating with a plurality of port sampling clock rates

A logical pipeline or logical hybrid pipeline is used for an xDSL communication system, and particularly for processing DMT symbols. This flexible arrangement permits easy and efficient sequencing of DMT symbols for transmit/receive tasks, and for multiple ports, since the pipeline resources can be shared or allocated as needed to support a particular data transmission. Each stage in the pipelines works on input data objects, and creates output data objects in the same format for use by other stages. The data objects are based on DMT symbols, so this facilitates intelligent control and sequencing of a DMT data transmission. The combination of the pipeline and the tailored data objects permits an implementation of a customized xDSL symbol processor.

xDSL symbol processor and method of operating same

A digital communications link, protocol and related circuits are provided which use an embedded control channel for transferring control information between different sections of an xDSL system, including within a personal computer. The control channel is included as part of a data frame structure that is suited for a multi-channel communication system, including in an xDSL communications environment.

DSL link with embedded control and multi-channel capability

A new type of pipeline, generally referred to as a logical pipeline is disclosed. A logical pipeline generaly includes a set of hardware based pipeline stages that exchange data through a common pipeline memory, instead of only through intermediate fixed physical buffers. Thus, operational data is retrieved and stored by each stage using a single memory, and this permits flexible and programmable forms of pipelines that can be adapted as needed in response to a desired computation task. A common pipeline clock initiates processing of the data. Another variation is disclosed in the form of a logical 'hybrid' pipeline, consisting of both software and hardware based pipeline stages, that are used to perform a set of computations in an interleaved fashion. In this manner, a data item can be handled first by a hardware pipeline stage, followed immediately by a software pipeline stage, etc. Furthermore, in a communications system, this arrangement permits processing for a number of ports to be distributed so that at any pipeline clock period, both hardware and software stages can be operating on different ports, or different communication tasks (i.e., transmit and receive).

Logical pipeline for data communications system

A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs acheivable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field. A system constructed in this fashion is highly gate efficient and cost effective, so that a multiport system can be put on single SOC integrated circuit.

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San Jose, CA, United States of America

Ming-Kang Liu