United Microelectronics Corp.

Global Unichip Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Jing Ho

Le-Tien Jung

Shih-Lun Chen

Wen-Tai Wang

Shi-Hao Chen

Kuey-Lung Hsueh

Yu-Ming Sun

Hsin-Wo Fang

An integrated circuit includes a main clock tree, a reference clock trunk, a reference clock buffer and a calibration circuit. The main clock tree transmits a main operation clock to an internal node via serially-coupled buffers to form a local clock at an internal node. The reference clock buffer transmits a main reference clock via the reference clock trunk to form a reference clock at a terminal node. The calibration circuit compares phases of the local clock and the reference clock to accordingly generate a control signal, so the main clock tree can adjust phase of the local clock according to the control signal.

Integrated circuit

The present invention discloses an efficient way to read data from a memory device by aligning an internal clock of the memory interface circuit with the read data strobe signal from the memory device by delaying the internal clock along with control signals for reading the memory device before transmitting them to the memory device, wherein the internal clock of the memory controller can sample the read data from the memory device directly without using a FIFO device between the internal clock and the read data strobe so as to reduce latency of reading data from the memory device. For example, the memory device can be a double-data-rate (DDR) DRAM device, and the control signals includes command and address signals of the DDR DRAM device.

Apparatus for reducing read latency by adjusting clock and read control signals timings to a memory device

A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

Signal delay circuit and signal delay method

For a negative-powered IC, an ESD protection circuit includes a negative voltage clamping circuit configured to provide a path for discharging ESD transient currents associated with different negative power supplies of the IC.

ESD protection circuit for negative-powered integrated circuit

The invention provides an electronic device for reducing simultaneous switching noise (SSN). The electronic device includes: a driver, driving an external device according to an input signal, and including: an input end, receiving the input signal; a positive output end, coupled to an external capacitor of the external device; and a negative output end, coupled to a variable capacitor; and a loading calibration circuit, generating an adjusting signal to adjust a first capacitance of the variable capacitor so as to make the first capacitance approximately equal to a second capacitance of the external capacitor.

Apparatus for reducing simultaneous switching noise

A delay locked loop (DLL) circuit for improving jitters includes a detecting unit, a master controller, a slave controller, first and second variable delay lines, first and second dummy loads, and a processor. The master controller generates a first control signal in response to a detecting signal. The slave controller generates a second control signal in response to the detecting signal. The first variable delay line delays a reference clock in response to the first control signal so as to generate a delay clock. The processor is configured to selectively generate a slave input signal, wherein if the processor does not generate the slave input signal, the processor makes the second dummy load draw a load current from the slave controller.

Delay locked loop (DLL) circuit for improving jitter

A chip with programmable input/output (I/O) circuits has a plurality of layout layers including a plurality of same layouts in a plurality of positions of the layout layers so as to implement a plurality of sub-circuit cells with the same layout, and at least a connection layer having different layouts corresponding to the different positions of the layout layers so that the sub-circuit cells in different positions implement different circuit functions.

Input/output circuits with programmable option and related method

An integrated circuit (IC) having an electrostatic discharge (ESD) protection circuit therein is provided. The IC comprises a plurality of bonding pads, a plurality of ESD units, a first ESD bus and a second ESD bus. The first ESD bus has no direct connection with any power pad of the IC. Each ESD unit comprises a first diode, a second diode and an ESD clamping device. Due to the one-to-one correspondent of each bonding pad with an ESD unit, the present invention ensures ESD continuity through a continuous charge dissipation path no matter what kind of pin-to-pin ESD test the IC is undergoing or how many power sources the IC has. In addition, a bonding pad over active circuitry (BOAC) structure can also be deployed in the present invention to provide a better ESD protection for the whole IC chip.

Integrated circuit with ESD protection circuit

A method of determining the correctness of a DRAM redundancy repair. The method is capable of detecting whether a redundancy repair has been properly conducted. The method includes illuminating a die on a wafer with a convergent light beam and observing the physical bit map produced after illumination on a screen. When the convergent light beam aims at a defective array, two semicircular shaped images appear on the screen. When the convergent light beam aims at a redundancy element used in a redundancy repair, a bright line appears on the screen. Through gauging the relative positions between the bright line and the pair of semicircular images, proper replacement by a redundancy element can be ascertained.

Method of analyzing DRAM redundancy repair

A method of manufacturing a ROM cell. A DRAM cell is provided. An ONO (oxide-nitride-oxide) stacked layer is used as a dielectric film of a capacitor of the DRAM cell. When a supply power is over 6 volts, the dielectric layer would be breakdown so that leakage is occurred between a lower electrode and an upper electrode of the capacitor. The DRAM cell, which can be used as a ROM cell, is thus readout as a stock at fault to stock a logic state of &ldquo;1&rdquo; or &ldquo;0&rdquo;. The stored data as &ldquo;1&rdquo; or &ldquo;0&rdquo; is depended on voltage of the upper electrode (V ) and a voltage of the bit line (V ). If V >V , the breakdown of the dielectric film would make the cell stock at &ldquo;1&rdquo;, and a normal DRAM cell is stocked at &ldquo;0&rdquo;, and vice versa.

Method of manufacturing mask read-only memory cell

A method of manufacturing a ROM cell. A DRAM cell is provided. An ONO (oxide-nitride-oxide) stacked layer is used as a dielectric film of a capacitor of the DRAM cell. When a supply power is over 6 volts, the dielectric layer would be breakdown so that leakage is occurred between a lower electrode and an upper electrode of the capacitor. The DRAM cell, which can be used as a ROM cell, is thus readout as a stock at fault to stock a logic state of &ldquo;1&rdquo; or &ldquo;0&rdquo;. The stored data as &ldquo;1&rdquo; or &ldquo;0&rdquo; is depended on voltage of the upper electrode (V,) and a voltage of the bit line (V,). If V,>V,, the breakdown of the dielectric film would make the cell stock at &ldquo;1&rdquo;, and a normal DRAM cell is stocked at &ldquo;0&rdquo;, and vice versa.

A semiconductor memory device and a method for mending a failed memory cell by directly programming a fuse memory cell. Using a tester to program the fuse memory cell directly, a laser machine is not required. In addition, to move the wafer for fuse allocation is not required either, so that the consumption in time and cost can be greatly reduced. Even after the package is complete, the repairing work can still be performed. In addition, whether the voltage source is connected or disconnected, the failed address information is kept and stored without being lost. A self-repair for self-test can thus be applied.

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Taipei, Taiwan

Ming-Jing Ho