Lsi Corporation

Western Digital Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Seagate Technology Incorporated

Micron Technology Incorporated

Other

Intel Corporation

Stmicroelectronics S.r.l.

Seagate Technologies, Inc.

Ming Jin

Fan Zhang

Shaohua Yang

Haitao Xia

Wu Chang

Erich Franz Haratsch

George Mathew

Jun Xiao

Jongseung Park

Bruce Alexander Wilson

Ilya V Karpov

Myint Ngwe

Lei Chen

Scott M Dziak

Jinwook Lee

Yang Han

Carl E Forhan

Timothy W Swatosh

Dahua Qin

Timothy B Lund

Parviz Rahgozar

Kurt J Worrell

Liu Li

Steven L Cochran

Narahari Ramanuja

Weijun Tan

Johnson Yen

Yuan Xing Lee

Jeffrey Paul Grundvig

Chung-Li Wang

Richard Rauschmayer

Changyou Xu

Kent Douglas Anderson

Xuebin Wu

Yudong Kim

Daniel Xu

Yongke Sun

Dean V Dang

Galvin Chia

Noureddine Kermiche

Jianzhong Huang

Teik Ee Yeo

Shafa Dahandeh

Jason S Goldberg

Quek Leong Choo

Abdel-Hakim S Alhussien

Madhusudan Kalluri

Lanlan Gu

Prakash Balasubramaniam

David Loh

HiauChoon Kee

Kek Ming Chua

Hiau Choon Kee

Alvin W Tan

MingYou Hu

Dennis P O'Connor

Adbel Hakim S Alhussien

King S Goh

William J Ledden

AbdelHakim S Alhussein

Jonathan Dykhuis

Shyam Prasad Teegapuram

Zhenyu Sun

Erman Bengu

This disclosure includes back pattern counter measures for solid state drives. Embodiments described herein include setting and applying read threshold offsets according to flags set based on an amount of data stored within a memory block (e.g., an 'openness' of the block). The flag is implemented during read commands to account for shifts in voltage distribution of open blocks. A value of the flag may be chosen based on a number of word lines included in the block that store data. The read threshold offsets may further be based on at least one of the set flag or an age of a respective NAND cell.

Back pattern counter measure for solid state drives

Disclosed is a system and method for providing program verify adaptation for flash memory. The method includes performing an adjustment iteration, which includes accessing error counts for respective N states of a plurality of memory cells, applying a weighting to the error counts based on a binary data coding for the N states, determining a state Smin of the N states having a minimum error count Emin from the error counts, determining a state Smax of the N states having a maximum error count Emax from the error counts, determining a difference between the Emax and the Emin satisfies an error count threshold, and adjusting, by a predefined value, a respective program verify offset of a lowest state from Smin and Smax, and of each state between Smin and Smax in the N states, wherein the adjusting is a decrement when Smin is less than Smax and an increment otherwise.

Program verify adaptation for non-volatile memory

Program verify adaptation for memory devices

Program verify adaptation for flash memory

One example of erasure-assisted error correction code (ECC) decoding can include reading a codeword with a first trim level, reading the codeword with a second trim level, and reading the codeword with a third trim level. A first result from reading the codeword with the first trim level, a second result from reading the codeword with the second trim level, and a third result from reading the codeword with the third trim level can be accumulated. An erasure of a detected unit sequence can be computed. The detected unit sequence can be modified by changing a unit in a position of the detected unit sequence corresponding to a position of the erasure. The modified detected unit sequence can be ECC decoded.

Apparatuses and methods for erasure-assisted ECC decoding

Variations of the Nelder-Mead direct search method are employed to find read channel parameter settings in a discrete field having three or more dimensions. The three or more dimensions correspond to read channel parameters, at least some of which are highly correlated. The steps of the Nelder-Mead method are executed according to a methodology to arrive at substantially optimal parameter settings for a read channel, even where a discrete function defining parameter outcomes is noisy. In some embodiments, dimensional collapse, considered inefficient in a two-dimensional field, is allowed in order to reach an optimal solution in a greater-than-two-dimensional field.

Multi-dimensional optimization of read channel

Systems and methods for data processing particularly related local iteration randomization in a data decoding circuit. In some cases a data processing system may include: a layered data decoding circuit, a value generator circuit, and a selector circuit. The layered data decoding circuit is configured to iteratively apply a data decoding algorithm up to a selected number of times to a decoder input to yield a decoded output in accordance with a layer order. The value generator circuit is operable configured to generate an adjusted number of times where the adjusted number of times is less than a default number of times. The selector circuit is operable configured to select one of the default number of times and the adjusted number of times as the selected number of times.

Systems and methods for enhanced local iteration randomization in a data decoder

Various approaches, methods, systems, circuits and devices for channel bit density estimation.

Systems and methods for channel target based CBD estimation

Methods and apparatus are provided for detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and decoding the plurality of bits using a binary decoder. The non-binary log likelihood ratio captures one or more of intra-page correlations and/or intra-cell correlations. A least significant bit and a most significant bit of a given cell can be independently converted and/or jointly converted to the non-binary log likelihood ratio.

Detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window

The present inventions are related to systems and methods for iterative data processing scheduling. In one case a data processing system is disclosed that includes a data detector circuit and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output. The data decoder circuit is operable to repeatedly apply a data decoding algorithm to the detected output to yield a decoded output over a number of passes, where the number of passes is within an allowable number of local iterations selected based at least in part on a read gate signal.

Systems and methods for gate aware iterative data processing

A disk drive is disclosed including a disk having a plurality of sectors, and a head actuated over the disk. A defect threshold is initialized, and a first sector is read to generate a first read signal. The first read signal is processed to detect a defect in the first sector relative to the defect threshold. After detecting the defect, the defect threshold is adjusted and the first sector is reread to generate a second read signal. The second read signal is processed to detect the defect in the first sector relative to the adjusted defect threshold.

Disk drive adjusting a defect threshold when scanning for defective sectors

The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol.

Method and system for generation of a tie-breaking metric in a low-density parity check data encoding system

Various embodiments of the present invention provide systems and methods for media defect detection.

Systems and methods for enhanced media defect detection

Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.

Systems and methods for detector side trapping set mitigation

A method, apparatus, and controller for acquiring and tracking at least one threshold voltage of at least one cell of at least one flash chip. The method can include acquiring the at least one threshold voltage of a particular cell of the at least one flash cell. The method can further include performing at least one threshold voltage adjustment iteration.

Threshold acquisition and adaption in NAND flash memory

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Fremont, CA, United States of America

Ming Jin