Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

United Microelectronics Corp.

Silicon Storage Technology, Inc.

Actrans System Incorporation, USA

Ming-Jer Chen

Der-Tsyr Fan

Chiou-Feng Chen

Prateep Tuntasood

Chin-Shan Hou

Caleb Yu-Sheng Cho

Po-Chin Hsu

Chuan H Liu

Tien-Yu Wu

Wei-Chen Shen

Mainn-Gwo Chen

Yen-Bin Gu

Chu-Chang Lin

Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Self-aligned split-gate NAND flash memory and fabrication process

A capacitor having a low voltage coefficient, even though one electrode is a semiconductor and one is a metal, is described. Two parallel plate capacitors are formed side by side and then cross-connected. The bottom plate of one of the capacitors is connected to the top plate of the other capacitor, and vice versa. This arrangement causes the two capacitors to be polarized in opposite directions at all times so that the individual voltage coefficients cancel each other and give the combined structure a value that is about 2 ppm V. A process for manufacturing this capacitor is also described.

Cross-coupled capacitors for improved voltage coefficient

An electrostatic discharge protective circuit formed by use of a silicon controller rectifier is coupled to an input port and an internal circuit for discharging electrostatic charges on the input port to ground. When the electrostatic charges are applied on the input port, a punch-through effect is created between a first P-type diffusion region and a second N-type diffusion region to turn on a parasitic NPN bipolar junction transistor. At the same time, a voltage is applied on a gate of the MOS transistor via a small-signal equivalent capacitor to turn on itself, thereby discharging the electrostatic charges. Accordingly, the trigger voltage of the silicon controller rectifier can be efficiently lowered to improve the electrostatic discharge protective capability of the silicon control rectifier.

Electrostatic discharge protective circuit formed by use of a silicon

A capacitor having a low voltage coefficient, even though one electrode is a semiconductor and one is a metal, is described. Two parallel plate capacitors are formed side by side and then cross-connected. The bottom plate of one of the capacitors is connected to the top plate of the other capacitor, and vice versa. This arrangement causes the two capacitors to be polarized in opposite directions at all times so that the individual voltage coefficients cancel each other and give the combined structure a value that is about 2 ppm/V. A process for manufacturing this capacitor is also described.

This invention deals with the problem of an error voltage in a MOSFET analog switch sample and hold circuit caused by the turn off charge in the MOSFET analog switch. The invention provides a compensating circuit which can be adjusted to exactly compensate for the turn off charge which causes the error so that the error can be reduced to zero or nearly zero. The compensating circuit can be used in both open loop and closed loop sample and hold circuits. The compensating circuit can be used in combination with a Miller feedback circuit for eliminating the error voltage.

Compensating circuit for MOSFET analog switches

Growing community of inventors

Hsinchu, Taiwan

Ming-Jer Chen