Realtek Semiconductor Inc.

Ming-Je Li

Chi-Shun Weng

Meng-Han Hsieh

Liang-Wei Huang

Ting-Fa Yu

Shieh-Hsing Kuo

Rong-Jen Chang

Kai-Yi Fang

Chien-Chih Chen

Ta-Chin Tseng

Jih-Nung Lee

Ming-Yuh Yeh

Shian-Ru Lin

Hsiang-Huang Wu

A method applied to a wired network including a first network device and a second network device is disclosed. The first and second network devices each include a first set of connection ends and a second set of connection ends. Firstly, the first network device transmits a specific signal pattern through its first set and second set of connection ends. Then, the first network device detects whether a signal is received at its first set and second set of connection ends. If it is determined that a signal is not received at the first set connection ends while a signal is received at the second set connection ends, the first network device determines that its second set of connection ends is not correctly coupled to the second set of connection ends of the second network device.

Method for determining connection status of wired network

An integrated circuit is disclosed, including at least one configuration pin, an interface circuit, a detecting circuit, a determining circuit and a storage unit. A physical layer circuit of the invention not only increases the flexibility of setting PHY addresses, but also reduces the number of configuration pins.

Circuit and method for setting data and their application to integrated circuit

A network processor includes a transceiver circuit, a network data processing unit, and a clock signal control unit. The transceiver circuit transmits and receives a network signal, compares a voltage level of the network signal with a threshold value, outputs a comparison result, and operates under a first clock signal. The network data processing unit is coupled to the transceiver circuit to process the network signal, and operates under a second clock signal different from the first clock signal. The clock signal control unit disables supply of the second clock signal to the network data processing unit when the voltage level is smaller than the threshold value, and enables supply of the second clock signal to the network data processing unit when the voltage level is not smaller than the threshold value. An energy saving method for a network processor is also disclosed.

Network processor and energy saving method thereof

A power-saving network apparatus includes a MAC and a PHY. The PHY includes a transmitter and a receiver. The transmitter executes the operations of: transmitting a data signal to a remote network apparatus according to output packets of the MAC when the transmitter enters a normal state; transmitting an idle signal to the remote network apparatus when the transmitter enters an idle state; transmitting an indication signal to the remote network apparatus to notify it to enter a low power state, wherein the indication signal is different from the idle signal; entering the idle state or the normal state from the low power state in response to at least one of a predetermined period and a transmitting enable signal.

Power-saving network apparatus having physical layer circuit capable of entering low power state

A master device for an Ethernet system is disclosed. The master device includes a receiver, a buffer, a phase lock loop unit, and a transmitter. The receiver is used for generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode. The buffer is coupled to the receiver for accumulating the phase adjustment data and outputting a phase adjustment value. The phase lock loop unit is coupled to the buffer for adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock. The transmitter is used for transmitting initialization data to the slave device according to the output clock.

Ethernet system and related clock synchronization method

A device for allocating a number of taps of a designated finite impulse response filter is disclosed. The device comprises a plurality of designated finite impulse response filters having fixed number of taps, a plurality of allocation finite impulse response filters having fixed number of taps, a control unit and an estimate unit. Depending on intensities of responses to interferences, at least one of the allocation FIR filters may be coupled in series to any one of the designated finite impulse response filters, thereby to provide a signal having excellent quality.

Order adaptive finite impulse response filter and operating method thereof

A method for generating a spread spectrum clock includes the steps of providing a reference clock having a reference period; generating a plurality of output clocks respectively having different phases according to the reference clock; generating a first/second control signal according to the reference clock and a spread spectrum clock and starting a first/second duration accordingly; during the first/second duration, outputting a first/second selecting signal representing a first/second predetermined sequence according to the first/second control signal, wherein the second predetermined sequence is a substantial reversed sequence of the first predetermined sequence; and during the first/second duration, sequentially outputting some or all of the output clocks as the spread spectrum clock according to the first/second predetermined sequence.

Method for generating a spread spectrum clock and apparatus thereof

The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test signal through the shared pins. Pins necessary for the microelectronic device are therefore reduced.

Microelectronic device and pin arrangement method thereof

A configuration setting circuit and the method thereof, in which the configuration setting circuit includes a clock generator, a plurality of terminals, and a frequency detector coupled to a terminal. The clock generator is used to generate multiple clock signals with different frequencies, and output through the terminals. One input signal is inputted to the frequency detector through the terminal coupled to the frequency detector, so that the frequency detector can output at least two-bit configuration signal corresponding to the frequency of the input signal to set the operation mode.

Growing community of inventors

Yilan County, Taiwan

Ming-Je Li