United Microelectronics Corp.

Ming-I Chen

Chih-Hua Lee

Jui-Hsiang Pan

Fang-Mei Chao

Yung-Chieh Fan

Ying-Ko Chin

Yi-Chiao Wang

A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants.

CMOS structure and latch-up preventing method of same

The Complementary Metal-Oxide Semiconductor (CMOS) transistor of the present invention includes deep halo doped regions in the substrate. The fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.

Method of fabricating CMOS transistor

The CMOS transistor of the present invention includes deep halo doped regions in the substrate, which can avoid the occurrence of latch-up. In addition, the fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.

CMOS transistor

A high voltage metal oxide semiconductor device including a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

High voltage metal oxide semiconductor device

A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

Method of fabricating high voltage metal oxide semiconductor device

Fabricating method of a high voltage metal oxide semiconductor device

A method for manufacturing a photodiode CMOS image sensor. A first well and a second well are formed in a first type substrate. An isolation layer is formed over the first well and the second well. At the same time, an isolation layer is formed over another region to pattern out an active region for forming the photodiode. A protective ring layer is formed over the peripheral area of the photodiode active region. A first gate structure and a second gate structure are formed above the first well and the second well respectively. A first type source/drain region and a second type source/drain region are formed in the first well and the second well respectively. Concurrently, a second type heavily doped layer is formed in the first type substrate inside the area enclosed by the protective ring layer. A high-energy ion implantation is carried out to form a second type lightly doped layer in the first type substrate just outside the second type heavily doped layer. The second type lightly doped layer has a thickness much greater than the second type heavily doped layer.

Method of manufacturing photodiode CMOS image sensor

A CMOS structure having a silicon dioxide outer ring around the sense region. The CMOS sense structure has a substrate, a n,region, a n,region, an isolation region, a field implant region and a silicon dioxide outer ring region. The n,region is formed in the substrate, and the n,region is formed within the n,region. The isolation region is formed in the substrate next to the edge of the n,region. The field implant region is formed under the isolation region. The silicon dioxide outer ring region is formed over the n,region, a portion of the isolation region and a portion of the n,region. The silicon dioxide outer ring can prevent surface leakage that is caused by etching and lengthening the distance from the n,region to the field implant region so that edge junction leakage is reduced.

CMOS sense structure having silicon dioxide outer ring around sense region

A method for increasing isolation ability is disclosed. A shallow trench into semiconductor device is formed on a wafer. Therefore the wafer owns a semiconductor substrate and wherein a first gate oxide layer is formed on the semiconductor substrate. A nitride layer is formed on the gate oxide layer. Then the method will include the following statement. Firstly a deep well layer is formed into the semiconductor substrate. Then patterning oxide layer and the nitride layer is carried out. Thereafter trenches is formed. The portion of silicon nitride layer and gate oxide layer will be etched according to the pattern of the gate oxide layer and the nitride layer. Sequentially first implanting a couple of device cell into the deep well of semiconductor substrate is achieved. Then the couple of device cell is annealed. The whole silicon nitride layer is removed. Not only the second implanting cell device will be obtained but also the third implanting cell device will be achieved. The first gate oxide layer is removed. A second gate oxide, a polysilicon layer and a tungsten silicide layer are in sequence deposited. Then the polysilicon gate is defined. The polysilicon gate is etched that abuts between the couple of cell device. Cell isolation implanted behind the trench wherein the isolation is formed thus excited between said couple of cell device. The cell device and cell isolation both are annealed. Consequentially a silicon oxide is conformably deposited in order to fulfill the trench. Finally the surface of silicon oxide is planarized.

Method for increasing isolation ability using shallow trench

A method for forming a metallic reflecting layer in a semiconductor photodiode including a CMOS photodiode to enhance the sensitivity by filling a trench formed in the isolation next to the depletion region of the semiconductor photodiode with high reflectivity metal. The metal filled in the trench is used as a metallic reflecting layer to increase the number of photons reaching the depletion region by reflecting part of the aslope incident photons. An insulator is formed on the top of the metallic reflecting layer to electrically insulate the metallic reflecting layer from other conducting device formed by the follow-up process.

Method for forming a metallic reflecting layer in a semiconductor

A CMOS sensor structure and method of manufacture that includes the fabrication of a special shallow trench isolation structure. Besides isolating the active region for forming the CMOS sensor device, the shallow trench isolation structure has a special reflective plug embedded inside capable of reflecting incoming light onto the sensitive region of the CMOS sensor. Hence, the interactive length of incoming light with the light sensitive region can be increased, thereby increasing the contrast ratio and light sensitivity of the CMOS sensor.

Growing community of inventors

Hsinchu, Taiwan

Ming-I Chen