Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Hui Shen

Chia-Shiung Tsai

Shih-Chang Liu

Chi-Hsin Lo

Yi-Shin Chu

Tsun Kai Tsao

Jui-Yu Pan

Chung-Jen Hwang

A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.

Structure for flash memory cells

Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a semiconductor substrate comprising a floating gate, a charge trapping dielectric layer is formed, and a control gate is formed. The floating gate structure has vertical sidewalls, one side adjacent a source region and one side adjacent a drain region. A symmetric sidewall dielectric is formed over the floating gate structure on both the source side and drain side regions. An asymmetric dielectric layer is formed over the drain side sidewall only. The use of the asymmetric sidewall on the drain side sidewall provides improved RTD immunity. Methods for forming the structure are disclosed.

Reverse disturb immune asymmetrical sidewall floating gate devices

A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

Gated semiconductor device and method of fabricating same

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Dounan Town, Taiwan

Ming-Hui Shen