Lattice Semiconductor Corporation

Bandspeed, Inc.

Ming Hui Ding

Om P Agrawal

Barry Britton

Jun Zhao

Xiaojie He

Sajitha Wijesuriya

Fulong Zhang

Satwant Singh

William B Andrews

John Schadt

Wei Han

Zheng Chen

Larry Fenstermaker

Sreepada Hegade

Anthony K Myers

David A Rhein

Warren L Ziegenfus

Gordon Hands

Ben William Jones

Ravindar Mohan Lall

Joel Coplen

John “Jack” Morton

Joel Copien

Ravindar Lail

Ravindar Lall

Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.

Fast boot systems and methods for programmable logic devices

A wireless communications apparatus that it is useable as a spectrum analyzer and as a wireless receiver. The wireless communications apparatus has a radio circuit that is configured to receive EM radiation. Signal processing logic receives signals from the radio circuit based on the EM radiation. The signal processing logic has a receiver operational mode that processes the signals in accordance with a communication protocol and outputs data encoded in the signals to a host processor. The signal processing logic has a spectrum analyzer operational mode that generates frequency domain data and passes the frequency domain data to the host processor. The frequency domain data describe strength versus frequency of the EM radiation. The host processes the data in accordance with the configuration currently in use. Therefore, the wireless communications apparatus operates as a receiver in one operational mode and as a real-time spectrum analyzer in another operational mode.

Approach for spectrum analysis in a receiver

In one embodiment, a programmable logic device includes a plurality of programmable logic blocks and a plurality of slices within each of the programmable logic blocks. At least one programmable logic blocks includes a first slice not adapted to provide register functionality or RAM functionality, a second slice adapted to provide register functionality but not RAM functionality, and a third slice adapted to provide register functionality and RAM functionality. Control logic within the programmable logic block is adapted to provide control signals at the programmable block level and at the slice level.

Programmable logic device with multiple slice types

In one embodiment of the invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within a programmable logic block. A dual-slice logic block includes a first slice including at least two lookup tables (LUTs); a second slice including at least two LUTs; and a routing circuit coupled to each of the LUTs within the first and second slices. The routing circuit is adapted to share outputs of the dual-slice logic block among the LUTs. In another embodiment of the invention, the dual-slice logic block includes a second routing circuit coupled to each of the LUTs within the first and second slices. The second routing circuit is adapted to share inputs of the dual-slice logic block among the LUTs.

Dual-slice architectures for programmable logic devices

Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.

Area efficient routing architectures for programmable logic devices

In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.

Logic block control architectures for programmable logic devices

Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices having at least a first and a second slice each having at least a first lookup table. At least one of the programmable logic blocks includes at least a first logic block slice, a second logic block slice, and a third logic block slice, with the first logic block slice being a logic block slice type different from the second logic block slice, and the third logic block slice being a logic block slice type different from the first and second logic block slices. Control logic provides at a programmable logic block level bundled and/or unbundled control signals at a logic block slice level for at least two of the logic block slices.

Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.

Dual slice architectures for programmable logic devices

Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.

Programmable logic device architecture with multiple slice types

A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

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San Jose, CA, United States of America

Ming Hui Ding