Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Hui Chih

Wen-Chun Huang

Ru-Gun Liu

Chia-Ping Chiang

Wen-Li Cheng

Tsai-Sheng Gau

Ping-Chieh Wu

Hung-Chun Wang

Yu-Po Tang

Cheng-Kun Tsai

Ya-Ting Chang

Cheng Kun Tsai

Tsung-Yu Wang

Chih-Wei Hsu

Ken-Hsien Hsieh

Feng-Ju Chang

Hui En Yin

Chun-Hung Wu

Chii-Ping Chen

Tsong-Hua Ou

Wen-Hao Liu

Wei-Long Wang

Cheng-Hsuan Huang

Yung-Sung Yen

Wen-Ju Preet Yang

Gwan Sin Chang

Jiing-Feng Yang

Nian-Fuh Cheng

Ching-Hsu Chang

Pi-Tsung Chen

Wei-Chen Chien

Cheng-Lung Tsai

Chi-Ping Liu

Wen Hao Liu

Chia-Feng Yeh

Chih-Ming Lai

Dian-Hau Chen

Burn Jeng Lin

Hua-Tai Lin

Cheng-Cheng Kuo

Chien-Wen Lai

Kuei-Liang Lu

Ko-Bin Kao

Dong-Hsu Cheng

Wen-Chen Lu

Chin-Min Huang

Chia-Cheng Chang

Cherng-Shyan Tsay

Jia-Guei Jou

Chih-Chung Huang

Jeng-Shiun Ho

Sheng-Wen Lin

Bing-Syun Yeh

Josh J H Feng

Yong-Cheng Lin

Jau-Shian Liang

Yung-Pei Chin

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Method for coloring circuit layout and system for performing the same

Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Optical proximity correction methodology using pattern classification for target placement

The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.

Methodology for pattern density optimization

Embodiments of the present disclosure provide a method of generating mandrel patterns. A mandrel pattern is generated by constructing a boundary box, initiating a plurality of lead mandrels, and extending the lead mandrels across the boundary box. When a pattern region includes holes, portions of mandrels are removed from the holes after extension of the leading mandrels.

Methods for generating a mandrel mask

The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.

The present disclosure provides a method of performing optical proximity correction (OPC). An integrated circuit (IC) design layout is received. The design layout contains a plurality of IC layout patterns. Two or more of the plurality of IC layout patterns are grouped together. The grouped IC layout patterns are dissected, or target points are set for the grouped IC layout patterns. Thereafter, an OPC process is performed based on the grouped IC layout patterns.

Environmental-surrounding-aware OPC

A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.

Mandrel spacer patterning in multi-pitch integrated circuit manufacturing

The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.

A method of determining whether a layout is colorable includes assigning nodes to polygon features of the layout. The method includes designating nodes as being adjacent nodes for nodes separated by less than a minimum pitch. The method includes iteratively removing nodes having less than three adjacent nodes from consideration to identify a node arrangement, wherein all nodes in the node arrangement have at least three adjacent nodes. The method includes determining whether the layout is colorable based on the node arrangement. Determining whether the layout is colorable includes independently assessing each internal node of node arrangement to determine whether each internal node of the node arrangement is colorable. The method includes generating a colored layout design for fabrication of the semiconductor device if each internal node of the node arrangement is colorable; and modifying the layout if at least one internal node of the node arrangement is not colorable.

Method of determining whether a layout is colorable

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Luzhou, Taiwan

Ming-Hui Chih