Taiwan Semiconductor Manufacturing Comp. Ltd.

Mosel Vitelic Corporation

Grand Plastic Technology Corporation Taiwan

Ming-Huan Tsai

Yu-Lien Huang

Clement Hsingjen Wann

Chun-Fai Cheng

Hun-Jan Tao

Wei-Han Fan

Chi-Wen Liu

Yuan-Hung Chiu

Chun-Hsiang Fan

Han-Ting Tsai

Chii-Ming M Wu

Ju-Wang Hsu

Zhao-Cheng Chen

Hsueh-Chang Sung

Yimin Huang

Tsu-Hsiu Perng

Hui OuYang

Yen-Ming Chen

Li-Te S Lin

Chun-Feng Nieh

Tung Ying Lee

Hsien-Hsin Lin

Chi-Kang Liu

Yung-Ta Li

Shau-Lin Shue

Chao-Cheng Chen

Pinyen Lin

Chih-Wei Chang

Neng-Kuo Chen

Po-Chin Chang

Peng-Fu Hsu

Fang-Cheng Chen

Baw-Ching Perng

Sheng-Wen Yu

Haiting Wang

Pei-Yi Lin

Kun-Yen Lu

Chen-Hua Douglas Yu

Syun-Ming Jang Jang

Mei-Yun Wang

Jeng-Horng Chen

Huan-Just Lin

Chien-Hao Chen

Ka-Hing Fung

Ching-Feng Fu

Wei-Yuan Lu

Chung-Long Chang

Yu-Hsien Lin

Chu-Yun Fu

Han-Yu Lin

Yu-Rung Hsu

Ming-Jie Huang

Bing-Yue Tsui

Kuan-Chung Chen

Yi-Chen Lo

Chia-Shun Hsiao

Chih-Cheng Wang

Yi-Chun Huang

Yi-Shan Chen

Tsai-Chun Li

Chon-Shin Jou

Cheng-Ku Chen

Chun-Lin Chen

Kuan-Da Huang

Hsien-Ching Lo

Fung Ka Hing

Hui Ouyang

Cheng-Hua Yang

Mei-Ru Kuo

Ting-Sing Wang

Tsang Jiuh Wu

Ju Wang Hsu

Hsieh Yue Ho

Hsiao Shih-Yi

Kang Tsung-Kuei

Chih-Feng Huang

Jann-Shyang Liang

Chin-Hwa Hsieh

Ru-Chian Chiang

Yaun-Hung Chiu

Baw-Ching Peng

Jw-Wang Hsu

Yung-Yi Hsu

Yi-Tsai Yi

Ming-Ru Tsai

D T Lee

A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, where the metal gate structure is surrounded by an interlayer dielectric (ILD) layer, where gate spacers extend along opposing sidewalls of the metal gate structure; recessing the metal gate structure and the gate spacers below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first material over the metal gate structure and over the gate spacers; forming a second material over the first material, where an upper surface of the second material is level with the upper surface of the ILD layer; and removing a first portion of the ILD layer adjacent to the metal gate structure to form an opening that exposes a source/drain region at a first side of the metal gate structure.

Fin field-effect transistor device and method

A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

Capping structures in semiconductor devices

A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.

Semiconductor devices and methods of manufacturing thereof

A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

Semiconductor device having modified profile metal gate

A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.

Method of fabricating a semiconductor device having modified profile metal gate

A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.

Gate structure for semiconductor device

A method of forming a semiconductor device is provided. The method includes forming a recess in a substrate and forming a first dielectric layer in the recess. A portion of the first dielectric layer is removed. A second dielectric layer is formed over the first dielectric layer. A gate structure is formed over the second dielectric layer.

Method of forming a semiconductor device

A FinFET and methods for forming a FinFET are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin. The method also includes recessing a portion of the exposed sidewalls of the fin to form multiple recessed surfaces on the exposed sidewalls of the fin, wherein adjacent recessed surfaces of the multiple recessed surfaces are separated by a lattice shift. The method also includes depositing a gate dielectric on the recessed portion of the sidewalls of the fin and depositing a gate electrode on the gate dielectric.

FinFETs and methods for forming the same

An embodiment fin field effect transistor (finFET) includes a fin extending upwards from a semiconductor substrate and a gate stack. The fin includes a channel region. The gate stack is disposed over and covers sidewalls of the channel region. The channel region includes at least two different semiconductor materials.

Combination FinFET and methods of forming same

An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

Method of manufacturing strained source/drain structures

A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.

A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.

Replacement channels for semiconductor devices and methods for forming the same using dopant concentration boost

A method includes forming isolation regions in a semiconductor substrate, forming a first semiconductor strip between opposite portions of isolation regions, forming a second semiconductor strip overlying and contacting the first semiconductor strip, and performing a first recessing to recess the isolation regions. A portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin. A second recessing is performed to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing. The inter-diffusion region is then etched.

FinFETs with necking in the fins

Growing community of inventors

Zhubei, Taiwan

Ming-Huan Tsai