Via Technologies, Inc.

Ming-Hsun Hsu

Chien-Cheng Chang

Yu-En Tzeng

Ko-Yan Shih

Ying-Lang Chuang

Chu-Yu Hsiao

A method for saving electrical power for a physical layer (PHY) device including a plurality of sub-circuits is disclosed. The method includes the steps of outputting a plurality of link pulses, asserting a plurality of disabling signals between two adjacent link pulses for disabling the sub-circuits, respectively, and deasserting the disabling signals for enabling the sub-circuits, respectively. The disabling signals are asserted separately for disabling the sub-circuits at different time points. A physical layer device for use in a chip for saving electrical power is also disclosed.

Physical layer device and power-saving method for physical layer device

A multi-port network interface circuit and related control method. The network interface circuit has a plurality of PHY circuits, each of the PHY circuit is used for transmitting signals to a plurality of corresponding network nodes via different ports. Each of the PHY circuits scrambles signals transmitted at different ports with different seeds, and the network interface circuit resets different PHY circuits at different times such that each of the PHY circuits starts to transmit signals at a different time.

Multi-port network interface circuit and related method for scrambling codes of different ports with different seeds and resetting signal transmission of different ports at different times

A multi-port network interface circuit and relative control method. The multi-port network is used for transmitting a plurality of signals to different nodes (like terminals) of a network via multiple ports of the network interface circuit. The network interface circuit triggers the transmission of the signals of the different ports with clocks of different phases, such that transition of the transmitted signals of different ports will not occur at a same time.

Multi-port network interface circuit and related method for triggering transmission signals of multiple ports with clocks of different phases

A circuit for testing a chip. The chip has an intellectual product circuit module, and the circuit has a multiplexer controller, several registers and a MUX finite state machine controller to configure these registers in different states according to the test patterns. In the next state, a test activating signal is provided to the intellectual product circuit module. The intellectual product circuit module is then operated and tested according to the output of the registers.

Method and circuit for testing a chip

A network apparatus capable of automatically configuring connection polarity includes a random number generator of a plural order for generating a plurality of random numbers, and a plurality of connectors each of which is connected to a corresponding network cable. Each of the connectors includes a signal detector for detecting a network signal, for example, a fast link pulse or a normal link pulse from the corresponding network cable, and a polarity configurer coupled between the signal detector and the random number generator for selectively changing a connection polarity of a connector thereof in accordance with one of the random numbers generated by the random number generator when the signal detector fails to detect a network signal from the corresponding network cable.

Network apparatus capable of automatically configuring connection polarities and the operating method thereof

Physical layer device with output buffer for link pulse generator connected to cascaded power sub-circuts that receive a series of disabling signals

A testing device for checking a clock signal generated by a clock pulse generating circuit. The clock pulse generating circuit outputs a clock signal and a multiplied clock second signal. The testing device includes a reset circuit, a dividing unit and a mask circuit. The reset circuit receives a first reset signal and the clock signal and then generates a second reset signal synchronous with the clock signal. The second reset signal controls the dividing unit and the mask circuit. Inside the dividing unit, the multiplied clock signal is divided by an integral multiple to produce a divided clock signal. The divided clock signal is then passed to the mask circuit where uncertain portions of the third signal are blanketed to produce a masked clock signal. The masked clock signal is sent to a tester where cycle width of the masked clock signal is measured and first reset signal is sent to the reset circuit.

Growing community of inventors

Taipei, Taiwan

Ming-Hsun Hsu