Industrial Technology Research Institute

Ming-Hsueh Wu

Kun-Lun Luo

Yee-Wen Chen

Chen-An Chen

A device and a method for generating input control signals of a serialized compressed scan circuit are provided. A control signal generating device receives a test clock signal from a clock input port and a state enable signal from a state enable bus, and correspondingly generates a shift enable signal, a capture enable signal and a strobe signal. A clock gating device is coupled to the control signal generating device, and receives the shift enable signal, the capture enable signal and the strobe signal. When the shift enable signal is enabled, the clock gating device controls the test clock signal as a serialized scan clock signal. When the strobe signal or the capture enable signal is enabled, the clock gating device controls the test clock signal as a scan clock signal.

Device and method for generating input control signals of a serialized compressed scan circuit

A repairable multi-layer memory chip stack wherein each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.

Repairable multi-layer memory chip stack and method thereof

A test device for an SoC test architecture has a test input port, a test output port, a plurality of cores, a register, and a plurality of user defined logics. The register has a plurality of bits corresponding to the cores. Each of the user defined logics is connected to a corresponding bit of the register and a corresponding one of the cores. Each of the user defined logic receives a plurality of test control signals, and receives the corresponding bit of the register to change values of the test control signals. Outputs of each of the user defined logics are connected to the corresponding core to determine whether a test instruction of the corresponding core is or is not needed to be updated.

Test device and method for the SoC test architecture

A multi-chip stacked system and a chip select apparatus are provided. The chip select apparatus includes n ID code generators and n activation logic units. The first ID code generator generates a first ID code and a second seed code according to a first seed code, and an iID code generator connected to the (i&#x2212;1)ID code generator generates an iID code and an (i+1)seed code according to the iseed code. The ID codes generated by the ID code generators are different to each other. Each of the activation logic units has an activation code. The iactivation logic unit receives the iID code from the iID code generator. The iactivation logic unit activates the ichip when the iID code is complied with the activation code of the iactivation logic unit.

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Kaohsiung, Taiwan

Ming-Hsueh Wu