Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Hsiung Chiang

Cheng-Ming Wu

Wen-Chuan Chiang

Yu-Hua Lee

James Cheng-Ming Wu

Chue-San Yoo

Tse-Liang Ying

A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask. A passivation layer is deposited overlying the conductive layer and the dielectric layer. The integrated circuit device is completed.

Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids

A method for making crown capacitors using a new and improved crown etch window process for DRAM cells is described. After forming FETs for the memory cells, a planar first insulating layer (IPO-1) is formed and bit lines are formed thereon. A second insulating layer (IPO-2) is deposited, and a first etch-stop layer and a disposable insulating layer are deposited. Contact openings are etched in the layers to the substrate, and are filled with a polysilicon to form capacitor node contact plugs. The disposable layer is removed to expose the upper portions of the plugs extending above the first etch-stop layer. A second etch-stop layer is deposited and a thick insulating layer is deposited in which capacitor openings are etched over and to the plugs. The capacitor openings can be over-etched in the thick insulating layer because the plugs extend upward thereby allowing all the plugs to be exposed across the wafer without overetching the underlying IPO-2 layer that would otherwise cause capacitor-to-bit-line shorts when the bottom electrodes are formed in the capacitor openings.

Process for making new and improved crown-shaped capacitors on dynamic random access memory cells

A process for reducing the aspect ratio, for narrow diameter contact holes, formed in thick insulator layers, used to integrate logic and DRAM memory devices, on the same semiconductor chip, has been developed. The process of reducing the aspect ratio, of these contact holes, features initially forming, via patterning procedures, lower, narrow diameter contact holes, to active device regions, in the logic area, while also forming self-aligned contact openings to source/drain regions in the DRAM memory region. After forming tungsten structures, in the lower, narrow diameter contact holes, polycide bitline, and polysilicon capacitor structures, are formed in the DRAM memory region, via deposition, and patterning, of upper level insulator layers, and polysilicon and polycide conductive layers. Upper, narrow diameter openings, are then formed in the upper level insulator layers, exposing the top surface of tungsten structures, located in the lower, narrow diameter contact holes. The formation of upper tungsten structures, in the upper, narrow diameter contact openings completes the process of forming metal structures, in narrow diameter openings, with reduced aspect ratios, achieved via a two stage contact hole opening, and a two stage metal filling procedure.

Reduction of the aspect ratio of deep contact holes for embedded DRAM devices

A method using a two-step contact process for making word-line strapping on DRAM devices was achieved. The method replaces a single-step contact process in which it is difficult to etch the smaller contact openings. After partially completing the DRAM cells by forming gate electrodes and word lines having a first hard mask, a planar first insulating layer is formed. Capacitor node contact openings are etched and capacitors with a protective second hard mask are completed. A thin first photoresist mask with improved resolution is used to etch small first contact openings in the first insulating layer to the word lines, while the second hard mask protects the capacitors from etching. Tungsten plugs are formed in the openings, and an interlevel dielectric layer is deposited over the capacitors. A thin second photoresist mask with improved resolution is used to etch second contact openings to the tungsten plugs. The word-line strapping for the DRAM is completed by forming tungsten plugs in the second contact openings. Since the tungsten plugs are formed after forming the capacitors, they are not subjected to high-temperature processing that could adversely affect the DRAM devices. The two thin photoresist masks replacing a thicker photoresist mask used in the single-step process allow smaller contact openings to be etched.

Method for fabricating small-size two-step contacts for word-line

A method for forming a self aligned contact wherein a dielectric layer is formed directly on a conductive structure according the present invention. A semiconductor structure having a polysilicon conductive structure (such as a bit line) thereon is provided. A contact area is located on the semiconductor structure adjacent to the conductive structure. A dielectric layer, preferably composed of silicon oxide is formed over the conductive structure and the semiconductor structure. A top hard mask layer is formed over the dielectric layer. A contact opening is formed in the top hard mask layer and the dielectric layer using an etch selective to oxide over polysilicon, thereby exposing the contact region of the semiconductor structure adjacent to the conductive structure without etching through the conductive structure. A first lining dielectric layer, a second lining dielectric layer, and a third lining dielectric layer are sequentially deposited on the sidewalls of the contact opening and on the contact area of the semiconductor structure. The first and third lining dielectric layers are preferably composed of silicon dioxide and the third lining dielectric layer is preferably composed of silicon nitride. The third lining dielectric layer is anisotropically etched forming a second contact opening in the second lining dielectric layer over the contact area while leaving a spacer on the sidewall of the contact opening. The second lining dielectric layer and the first lining dielectric layer are anisotropically etched to expose the contact area of the semiconductor structure, while the spacer prevents erosion of the second lining dielectric layer and the first lining dielectric layer on the sidewall of the contact opening. The remaining spacer is removed, preferably using a buffered HF dip. A polysilicon contact layer is formed on the second lining dielectric layer and on the contact area of the semiconductor structure.

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Taipei, Taiwan

Ming-Hsiung Chiang