Macronix International Co., Ltd.

International Business Machines Corporation

Qimonda North America Corporation

Vxis Technology Corp.

Ming-Hsiu Lee

Feng-Min Lee

Po-Hao Tseng

Chao-I Wu

Yu-Hsuan Lin

Yen-Hao Shih

Yu-Yu Lin

Hsiang-Lan Lung

Tzu-Hsuan Hsu

Dai-Ying Lee

Wei-Chih Chien

Erh-Kun Lai

Chung H Lam

Yun-Yuan Wang

Ming-Chang Kuo

Chieh-Fang Chen

Tien-Yen Wang

Hang-Ting Lue

Bipin Rajendran

Feng-Ming Lee

Cheng-Hsien Lu

Matthew Joseph Breitwisch

Roger W Cheek

Shih-Hung Chen

Thomas Happ

Jan Boris Philipp

Wei-Chen Chen

Chao-Hung Wang

Chun-Hsiung Hung

Yu Zhu

Thomas Nirschl

Matthew Joseph BrightSky

Kuang Yeu Hsieh

Win-San Khwa

Yi-Chou Chen

Mark C Lamorey

Chun Hsiung Hung

Hao-Ming Lien

Simone Raoux

SangBum Kim

Philip L Flaitz

Kai-Chieh Hsu

Kuang-Hao Chiang

Chiao-Wen Yeh

Yan-Ru Chen

Frieder Heinrich Baumann

Kuan-Chih Chen

Yuan-Hao Huang

Tian-Cih Bo

Hsin Yi Ho

Pei-Ying Du

Liang-Yu Chen

Chia-Hong Lee

Chih-Chieh Yu

Thomas Nirschi

Yang-Hong Shih

A high-level architecture for 3D-NAND based in-memory search provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. A search word is presented to a 3D-NAND memory along a direction of a bit line of the 3D-NAND memory. Each character of the word comprises a number of digits. Each digit is matched against respective layers of the 3D-NAND memory. Each digit is usable to represent one of a plurality of levels according to a selected encoding. Optionally, various lengths of words are accommodated via serial and/or parallel operations of one or more 3D-NAND memories.

High-level architecture for 3D-NAND based in-memory search

A non-volatile 3D memory search architecture provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. The architecture uses two word lines per unit of information of the searches and two memory devices per unit of stored feature to search against. The architecture uses respective bit lines of the non-volatile 3D memory array as respective matching lines for searching. Respective memory strings (e.g., NAND memory strings) of the non-volatile 3D memory array are usable to store respective data values, e.g., corresponding to elements to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. The architecture has applicability to comparing and sorting, in addition to searching in application areas such as artificial intelligence (AI) and big data.

Non-volatile 3D memory search architecture

An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.

In-memory computation device and in-memory computation method to perform multiplication operation in memory cell array according to bit orders

A universal memory for In-Memory Computing and an operation method thereof are provided. The universal memory includes at least one write word line, at least one unit cell and at least one read word line. The unit cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a transistor with adjustable threshold voltage. The gate of the read transistor is connected to the drain or the source of the write transistor. The read word line is connected to the drain or the source of the read transistor. The universal memory is used for a training mode and an inference mode. In the training mode and the inference mode, a weight is stored at different locations of the unit cell.

Universal memory for in-memory computing and operation method thereof

A memory device is provided. The memory device includes channel layers, word lines, memory layers disposed between the channel layers and the word lines, and memory cells defined at cross-points of the channel layers and the word lines. The memory device is configured for performing a first operation for m times and a second operation for n times, and m is equal to or larger than n. In the first operation, a first electric field is produced in a portion of the memory layers. The word lines are configured for producing a second electric field in the second operation in the portion of the memory layers, and a field direction of the second electric field is different from a field direction of the first electric field.

Memory device and method for operating the same

The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.

IMS memory cell, IMS method and IMS memory device

A storage device for generating an identity code, includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores several first data having several bits. The second storage circuit stores several second data having several bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, and simultaneously reads the first data from the first storage circuit to form a second sequence. The reading circuit includes a processing circuit which simultaneously receives the first sequence and the second sequence, selects a first portion of the second sequence to form a target sequence according to the first sequence, and outputs the target sequence to serve as an identity code. Logical values of the bits of the first data and the second data are randomly distributed or pre-defined by a user.

Storage device for generating identity code and identity code generating method

A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.

Semiconductor structure and method for manufacturing having the conductive portions isolated from each other by an insulating 2D material

A memory device and an intelligent operation method thereof are provided. The memory device includes a memory array, a signal generating circuit, an environment detecting circuit and an artificial intelligence (AI) circuit. The signal generating circuit is configured to generate an inputting signal. The environment detecting circuit is configured to detect at least one environment information. The AI circuit is connected among the memory array, the signal generating circuit and the environment detecting circuit. The AI circuit at least receives the inputting signal from the signal generating circuit, receives the environment information from the environment detecting circuit, receives a first performance information from the memory array, receives a second performance information from the AI circuit and outputs an ideal signal to the memory array according to the inputting signal, the environment information, the first performance information and the second performance information.

Memory device and intelligent operation method thereof

A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor, a second transistor and an inverter. The first search line is coupled to the second search line by the inverter.

Ternary content addressable memory and decision generation method for the same

A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.

A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.

Content-addressable memory and analog content-addressable memory device

A memory device includes a plurality of computing memory cells, each of which stores a weight value, receives an input value and generates an output value. Each of the computing memory cells includes a transistor connected to a bit line and a word line, receiving a sensing current through the bit line and receiving an input voltage through the word line. When the sensing current flows through the transistor, the computing memory cell generates a first voltage difference corresponding to the output value. The output value is equal to a product of the input value and the weight value.

Memory device for in-memory computing

A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

Method for manufacturing memory device

The application provides a memory device and an operation method thereof. The memory device includes: a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients; and at least one calculation unit. In receiving the input values, a first part and a second part of the memory cells generate a first part and a second part of the common source currents, respectively. The first part of the memory cells is electrically isolated from the second part of the memory cells based on a diagonal of the memory array. The at least one calculation unit calculates a first part and a second part of a local field energy of the model computation based on the first part and the second part of the common source currents.

Memory device and computing method thereof

Growing community of inventors

Hsinchu, Taiwan

Ming-Hsiu Lee