Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Hsing Tsai

Wei-Jung Lin

Hung-Wen Su

Chih-Wei Chang

Wei-Yip Loh

Hung-Hsu Chen

Chih-wei Chang

Shau-Lin Shue

Syun-Ming Jang Jang

Ken-Yu Chang

Chun-I Tsai

Sheng-Hsuan Lin

Ya-Yi Cheng

Chun-Hsien Huang

Li-Wei Chu

Shih-Wei Chou

Cheng-Tung Lin

Pin-Wen Chen

Chen-Hua Douglas Yu

Hong-Mao Lee

Yan-Ming Tsai

Da-Yuan Lee

Sheng-Hsiung Chen

Chun-Chieh Lin

Chen-Yuan Kao

Yu-Kai Chen

Cheng-Yen Tsai

Min-Hsiu Hung

Yu Shih Wang

Chien-Hsueh Shih

Wen-Jiun Liu

Teng-Chun Tsai

Ching-Hua Hsieh

Huan-Just Lin

Li-Ting Wang

Ching-Hwanq Su

Chi-Cheng Hung

De-Fang Chen

Yu-Sheng Wang

Ya-Lien Lee

Huang-Yi Huang

Hui-Cheng Chang

Ting-Chu Ko

Rueijer Lin

Chia-Han Lai

Hung-Chang Hsu

Yi-Hsiang Chao

Jing-Cheng Lin

Lin-Yu Huang

Weng Chang

Yu-Ting Lin

Chung-Chiang Wu

Shing-Chyang Pan

Hung-Yi Huang

Bing-Hung Chen

Liang-Yueh Ou Yang

Mei-Hui Fu

Mong-Song Liang

Yung-Cheng Lu

Jyu-Horng Shieh

Chii-Ming M Wu

Chih-Yuan Ting

Chia-Ching Lee

Yi-Hung Lin

Chih-Chien Chi

Hsueh Wen Tsau

Chien Chang

Chun-Yuan Chou

Shu-Cheng Chin

Chia-Pang Kuo

Sheng Hsiung Chen

Hsueh-Wen Tsau

Yao-Min Liu

Chih-Yi Chang

Chung-Chi Ko

Hsin-Yi Lee

Ying-Ho Chen

Hsien-Ming Lee

Chih-Hao Wang

Tsu Shih

Chia-Ying Lee

Hua-Tai Lin

Chien-An Chen

Jyh-Cherng Sheu

Sheng-Tsung Wang

Jih-Churng Twu

Jye-Yen Cheng

Ming-Shih Yeh

Chih-Hsiang Yao

Cheng-Cheng Kuo

Peng-Fu Hsu

Jeng-Shiou Chen

Ching-Yi Chen

Hui-Lin Chang

Chien Chung Huang

Yu-Shih Wang

Pi-Tsung Chen

Ya-Ling Lee

Cheng-Hui Weng

Chun-Wen Nieh

The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

Conductive feature formation and structure using bottom-up filling deposition

A pre-cleaning technique described herein may be used to remove native oxides and/or other contaminants from a semiconductor device in a manner in which the likelihood of chopping, clipping, and/or sidewall spacer thickness reduction is reduced. As described herein, a protection layer is formed on a capping layer over a gate structure of a transistor. A pre-cleaning operation is then performed to remove native oxides from the top surface of a source/drain region of the transistor. In the pre-cleaning operation, the protection layer is consumed instead of the material of the capping layer. In this way, the use of the protection layer reduces the likelihood of removal of material from the capping layer and/or reduces the amount of material that is removed from the capping layer during the pre-cleaning operation.

Semiconductor device pre-cleaning

A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.

Semiconductor device structure and method for forming the same

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes an epitaxial structure and a metal silicide layer. The epitaxial structure includes a semiconductor material. The metal silicide layer is disposed on the epitaxial structure. The metal silicide layer includes the semiconductor material, a first metal material and a second metal material. An atomic size of the first metal material is greater than an atomic size of the second metal material, and a concentration of the first metal material in the metal silicide layer varies along a thickness direction.

Semiconductor structure and manufacturing method thereof

A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

Contact features of semiconductor device and method of forming same

A method for manufacturing a semiconductor structure includes: forming a patterned structure which includes a first semiconductor portion and a second semiconductor portion, the first and second semiconductor portions having different materials; and performing an oxide formation process to oxidize the first and second semiconductor portions such that a first oxidation layer formed on the first semiconductor portion has a thickness less than that of a second oxidation layer formed on the second semiconductor portion.

Method for forming dual silicide in manufacturing process of semiconductor structure

Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

Contact with a silicide region

A method includes forming a first conductive feature in a first dielectric layer. A second dielectric layer is formed over the first conductive feature and the first dielectric layer. An opening is formed in the second dielectric layer. The opening exposes a top surface of the first conductive feature. The top surface of the first conductive feature includes a first metallic material and a second metallic material different from the first metallic material. A native oxide layer is removed from the top surface of the first conductive feature. A surfactant soaking process is performed on the top surface of the first conductive feature. The surfactant soaking process forms a surfactant layer over the top surface of the first conductive feature. A first barrier layer is deposited on a sidewall of the opening. The surfactant layer remains exposed at the end of depositing the first barrier layer.

Interconnect structure of semiconductor device

Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming a contact opening in an interlayer dielectric (ILD) layer disposed over an epitaxy source/drain region and forming a metal layer in the contact opening. The metal layer includes top portions, side portions, and a bottom portion, and a space is defined between the top portions of the metal layer. The method further includes performing a gradient metal removal process on the metal layer to enlarge the space, forming a sacrificial layer in the contact opening, recessing the sacrificial layer in the contact opening to expose a portion of the sidewall portions, removing the top portions and the exposed portion of the sidewall portions, removing the sacrificial layer, and forming a bulk metal layer on the bottom portion of the metal layer.

Methods of forming semiconductor device structures

A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

Semiconductor structure and method of forming the same

An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Ammonium fluoride pre-clean protection

A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

Phase control in contact formation

A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

A graphene liner deposited between at least one liner material (e.g., barrier layer, ruthenium liner, and/or cobalt liner) and a copper conductive structure reduces surface scattering at an interface between the at least one liner material and the copper conductive structure. Additionally, or alternatively, the carbon-based liner reduces contact resistance at an interface between the at least one liner material and the copper conductive structure. A carbon-based cap may additionally or alternatively be deposited on a metal cap, over the copper conductive structure, to reduce surface scattering at an interface between the metal cap and an additional copper conductive structure deposited over the metal cap.

Graphene liners and caps for semiconductor structures

Growing community of inventors

Chu-Pei, Taiwan

Ming-Hsing Tsai