Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Hsin Yu

Guang-Cheng Wang

Yu-Ren Chen

Kvei-Feng Yen

One or more systems and techniques for communicating a signal between a first chip and a second chip using one or more circuits are provided. If the signal corresponds to a first voltage, one or more voltages are provided to one or more locations and a capacitive load is charged using a pull-up driver that is connected to a power supply. If the signal corresponds to a second voltage, one or more voltages are provided to one or more locations and the capacitive load is discharged using a pull-down driver that is connected to ground. When the first chip is powered off, a fail-safe mode is provided by configuring a cross control circuit to generate a bias to control one or more transistors.

Controlling voltage at pad

An overdrive circuit includes a pull-up circuit and a pull-down circuit. The pull-down circuit includes first, second and third transistors electrically connected in cascode between an output node and a low voltage supply node. A capacitor is electrically connected from a gate electrode of the third transistor to a gate electrode of the first transistor. A first mono-directional bias device is electrically connected from a drain electrode of the first transistor to a gate electrode of the first transistor. A second mono-directional bias device is electrically connected from the gate electrode of the first transistor to a source electrode of the first transistor.

Overdrive circuits and related method

A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltages at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

3X input voltage tolerant device and circuit

A circuit structure includes a first isolation region, and a first dummy gate electrode over and vertically overlapping the first isolation region. First pickup regions of a diode are formed on opposite sides of the first isolation region, wherein sidewalls of the first pickup regions contact opposite sidewalls of the first isolation region. Second pickup regions of the diode are formed on opposite sides of a combined region of the first pickup regions and the first isolation region, wherein the first and the second pickup regions are of opposite conductive types. A well region is under the first and the second pickup regions and the first isolation region, wherein the well region is of a same conductivity type as the second pickup regions.

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Taichung, Taiwan

Ming-Hsin Yu