Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming Hsien Tsai

Tzu-Jin Yeh

Ruey-Bin Sheen

Jun-De Jin

Fu-Lung Hsueh

Hsieh-Hung Hsieh

Tsung-Hsien Tsai

Chewn-Pu Jou

Chih-Hsien Chang

Chun-Yu Lin

Sa-Lly Liu

Mao-Ruei Li

Chan-Hong Chern

Li-Wei Chu

Kun-Lung Chen

Huan-Neng Chen

Han-Ping Pu

Jen-Chou Tseng

Ming-Hsiang Song

Sen-Kuei Hsu

Tzong-Lin Wu

Tse-Hua Lu

Chin-Yi Lin

Sheng Hsiung Chen

Ping-Fang Hung

Chien-Min Lin

Yang-Chih Huang

Fan-Ming Kuo

Vincent Merigot

Tsu Shi

An IC includes power and reference nodes, a protection circuit, and a gate driver. The protection circuit includes a series of diode-configured enhancement-mode n-type HEMTs coupled between the power and reference nodes and including a voltage tap, a first enhancement-mode n-type HEMT including a gate coupled to the voltage tap and a source terminal coupled to the reference node, and a second enhancement-mode n-type HEMT including a gate coupled to a drain terminal of the first n-type HEMT and a source terminal coupled to the reference node. The gate driver includes a third enhancement-mode n-type HEMT including a gate coupled to a drain terminal of the second n-type HEMT, a fourth enhancement-mode n-type HEMT including a gate coupled to a source terminal of the third n-type HEMT and a source terminal coupled to the reference node, and an output terminal coupled to a drain terminal of the fourth n-type HEMT.

Driver circuit and method of operating the same

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

Circuit and method to enhance efficiency of semiconductor device

A circuit includes a temperature-sensitive voltage divider. The temperature-sensitive voltage divider includes a temperature-sensitive resistor and a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor. A temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor. Detection logic is coupled to the first node to generate a detection signal responsive to the temperature signal.

Temperature protection circuit

A circuit includes power supply and reference nodes, a protection circuit including a first output terminal and first and second series of n-type HEMTs coupled between the power supply and reference nodes, and a gate driver including a second output terminal and third through fifth series of n-type HEMTs coupled between the power supply and reference nodes. The first HEMT series controls a first node voltage responsive to a power supply node voltage, the second HEMT series controls a first output terminal voltage responsive to the first node voltage, the third HEMT series controls an internal signal on a second node responsive to the first output terminal voltage and to an input signal, the fourth HEMT series controls a third node voltage responsive to the internal signal, and the fifth HEMT series controls a signal at the second output terminal responsive to the internal signal and the third node voltage.

HEMT-based driver circuit and method of operating the same

A circuit includes a power supply voltage node having a power supply voltage level, a protection circuit that generates a first signal having first and second logical voltage levels based on the power supply voltage level, and a gate driver. The gate driver includes a first n-type HEMT between the power supply voltage node and a first node, a second n-type HEMT between the first node and a power supply reference node, and a DCFL circuit between the first node and an output terminal. A gate of the first n-type HEMT receives the first signal, a gate of the second n-type HEMT receives a second signal, and the DCFL circuit generates a third signal at the output terminal based on the second signal when the first signal has the first logical voltage level, and as a DC voltage level when the first signal has the second logical voltage level.

A filter structure includes a ground plane in a first metal layer of an integrated circuit (IC) package, a plate in a second metal layer of the IC package, a dielectric layer between the ground plane and the plate, the ground plane, the dielectric layer, and the plate thereby being configured as a capacitive device, and an inductive device in a third metal layer of the IC package. The inductive device is electrically connected to the plate, and the plate and the inductive device are configured to have a resonance frequency greater than 1 GHz.

Band stop filter structure and method of forming

Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.

Systems and methods for generating a controllable-width pulse signal

A filter structure includes a capacitive device and an inductive device. The capacitive device includes a ground plane in a first metal layer of an integrated circuit (IC) package, a plate in a second metal layer of the IC package, and a dielectric layer between the ground plane and the plate. The inductive device includes first and second conductive paths in a third metal layer of the IC package, each of the first and second conductive paths is electrically connected to the plate and has a width w, the first and second conductive paths are separated by a spacing s, and a ratio s/w has a value ranging from 1 to 2.

A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.

System and method for adjusting cycle of a signal

System and method for adjusting duty cycle of a signal

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Taipei, Taiwan

Ming Hsien Tsai