Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Hsien Lin

Kuo-Lung Hou

Chin-Shen Lin

Chung-Liang Cheng

Tsung-Cheng Wu

Chung-Hsing Wang

Kuo-Nan Yang

Ya-Chin Chiu

Sheng-Ying Wu

Yen-Yu Chen

Ta-Pen Guo

Wei-Jen Chen

Wan-Yu Lo

Meng-Xiang Lee

Wei-Chen Liao

Anthony Oates

Lun-Chieh Chiu

Chia-Tung Hsu

Shih-Lien Linus Lu

Cheng-Chin Lee

Kai-Fang Cheng

Hsiao-Kang Chang

Cherng-Shiaw Tsai

Tzo-Hung Luo

Che-I Kuo

Yung Hsin Lu

Yu-Lin Liu

Shau-Lin Shue

Chih-Wei Lin

Chia-Tien Wu

Wen-Hao Chen

Hsin-Yen Huang

Shao-Kuan Lee

Jian-Hong Lin

Hsin-Ping Chen

Chi-Yeh Yu

Chun-Yu Chen

Chun-Fu Chen

Kuang-Wei Yang

Ming-Hong Hsieh

Po-Wei Wang

Hsiao-Feng Lu

Ming-Che Chen

Chen-Hung Lin

Shou-Chung Lee

Wen-Tane Liao

Hai-Lin Lee

Chuan-Pu Chou

Chun Fu Chen

Kuo-Lung Huo

A chamber for a physical vapor deposition (PVD) apparatus includes a collimator configured to narrow filter sputtered particles into a beam, an electrostatic chuck configured to support a substrate in the chamber, a shield and a chamber plate. The chamber plate includes a nut plate portion having a plurality of nut plates and a plurality of cavities in the chamber plate that are configured to allow gas to ingress and egress, wherein the cavities and nut plates are provided in equal numbers. The chamber is configured to operate at a target pressure, and the number of nut plates and corresponding number of cavities are determined based on the target pressure.

Physical vapor deposition apparatus

To reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

Apparatus and method of manufacturing a semiconductor device

An interconnection structure includes a first dielectric layer, a first conductive layer disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, a second conductive layer disposed in the second dielectric layer in electrical contact with the first conductive layer, a third dielectric layer formed over the second dielectric layer, wherein the third dielectric layer comprises silicon carbon-nitride (SiCN) based material, and a resistor device disposed in the third dielectric layer.

Semiconductor interconnection structures comprising a resistor device and methods of forming the same

A semiconductor structure is provided. The semiconductor structure includes a substrate and a device region formed over the substrate. The semiconductor structure further includes an interconnect structure formed over the device region and a first passivation layer formed over the interconnect structure. The semiconductor structure also includes a metal pad formed over and extending into the first passivation layer and a second passivation layer formed over the first passivation layer. The second passivation layer includes a thermal conductive material, and the thermal conductivity of the thermal conductive material is higher than 4 W/mK.

Semiconductor structure with improved heat dissipation

Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

Threshold voltage tuning for fin-based integrated circuit device

A physical vapor deposition (PVD) system is provided. The PVD system includes a PVD chamber defining a PVD volume within which a target material of a target is deposited onto a wafer. The PVD system includes the target in the PVD chamber. The target is configured to overlie the wafer. An edge of the target extends from a first surface of the target to a second surface of the target, opposite the first surface of the target. A first portion of the edge of the target has a first surface roughness. The first portion of the edge of the target extends at most about 6 millimeters from the first surface of the target to a second portion of the edge of the target. The second portion of the edge of the target has a second surface roughness less than the first surface roughness.

Physical vapor deposition (PVD) system and method of processing target

An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.

Apparatus and methods for determining horizontal position of substrate using lasers

Embodiments are directed to a method of optimizing thickness of a target material film deposited on a semiconductor substrate in a semiconductor processing chamber, wherein the semiconductor processing chamber includes a magnetic assembly positioned on the semiconductor processing chamber, the magnetic assembly including a plurality of magnetic columns within the magnetic assembly. The method includes operating the semiconductor processing chamber to deposit a film of target material on a semiconductor substrate positioned within the semiconductor processing chamber, measuring an uniformity of the deposited film, adjusting a position of one or more magnetic columns in the magnetic assembly, and operating the semiconductor processing chamber to deposit the film of the target material after adjusting position of the one or more magnetic columns.

Physical vapor deposition process apparatus and method of optimizing thickness of a target material film deposited using the same

A semiconductor arrangement includes a heat source above an interconnect layer and below a heat conductor. The heat conductor is coupled to a heat sink by a thermally conductive bonding layer. Heat from the heat source is conducted through the heat conductor in a direction opposite the direction of the interconnect layer, through the thermally conductive bonding layer, and to a heat sink. The heat conductor includes an arrangement of dielectric layers, dummy metal layers, and dummy VIA layers.

Semiconductor arrangement and method of forming

An electrochemical plating apparatus for depositing a conductive material on a wafer includes a cell chamber. The plating solution is provided from a bottom of the cell chamber into the cell chamber. A plurality of openings passes through a sidewall of the cell chamber. A flow regulator is arranged with each of the plurality of openings configured to regulate an overflow amount of the plating solution flowing out through the each of the plurality of openings. The electrochemical plating apparatus further comprises a controller to control the flow regulator such that overflow amounts of the plating solution flowing out through the plurality of openings are substantially equal to each other.

Apparatus for electro-chemical plating

A plating system is provided. The plating system includes an electroplating chamber defining a plating region within which a wafer is plated. The electroplating chamber includes an inlet configured to introduce plating solution into the plating region of the electroplating chamber. The electroplating chamber includes an outlet configured to remove the plating solution from the plating region of the electroplating chamber. The plating system includes a barrier configured to inhibit removal of the plating solution from the plating region.

Plating system and method of plating wafer

An electrochemical plating apparatus for performing an edge bevel removal process on a wafer includes a cell chamber. The cell chamber includes two or more nozzles located adjacent to the edge of the wafer. A flow regulator is arranged with each of the two or more nozzles, which is configured to regulate an tap width of a deposited film flowing out through the each of the two or more nozzles. The electrochemical plating apparatus further includes a controller to control the flow regulator such that tap width of the deposited film includes a pre-determined surface profile. The two or more nozzles are located in radially or angularly different dispensing positions above the wafer.

A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.

Semiconductor structure

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Hsinchu County, Taiwan

Ming-Hsien Lin