Taiwan Semiconductor Manufacturing Comp. Ltd.

Amic Technology Corporation

Hermes Testing Solutions Inc.

Ming-Hsien Chen

Chih-Yu Tseng

Jao-Chin Cheng

Der-Chyang Yeh

Fu-Jier Fan

Ho-Yin Yiu

Wen-Kung Cheng

Yu-Jui Wu

Ruey-Yun Shiue

Chen-Peng Fan

Chie-Iuan Lin

Yao Hsiang Liang

Huang-Sheng Lin

Chao-Keng Li

Wen-Yuan Hsu

Chuan-Ying Lee

Jung-Chen Yang

Yi-Ting Chao

Aaron Wang

Richard Chen

Wen-Yu Ho

Yong-Sin Chang

Labo Chang

Hsiang-Wei Wang

Tzu-Chien Wang

Jia-Lin Lu

Chia-Pin Hung

The present invention provides a probe card. A module cap, on the probe card substrate, is designed to have a chute and the probe module can be installed on or uninstalled from the module cap via the chute. That simplifies the operations of assembling and disassembling the probe card and avoids positioning error.

Probe card

Disclosed is a CMOS image sensor with global shutters and a method for fabricating the CMOS image sensor. In one embodiment, a semiconductor device, includes: a light-sensing region; a charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact.

Method and apparatus for reducing light leakage at memory nodes in CMOS image sensors

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first conductive type well region in the substrate, and a second conductive type well region in the substrate. The first conductive type is different from the second conductive type. The first conductive type well region partially overlaps the second conductive type well region in an overlapping region. The semiconductor device structure also includes a source portion in the first conductive type well region and a drain portion in the second conductive type well region. The semiconductor device structure further includes a gate structure over the substrate and the overlapping region, and between the source portion and the drain portion. The semiconductor device structure further includes a first conductive type doping region in the first conductive type well region and the overlapping region.

Structure and formation method of semiconductor device structure with well regions

A semiconductor structure includes a transistor formed over a substrate. The transistor includes a transistor gate and at least one source/drain region. The semiconductor structure includes a pre-determined region coupled to the transistor. The semiconductor structure further includes a resist protection oxide (RPO) layer formed over the pre-determined region, wherein the RPO layer has a level of nitrogen of about 0.35 atomic % or less.

Image sensor having an RPO layer containing nitrogen

A semiconductor capacitor device. A dielectric layer is on a substrate. A stack capacitor structure is disposed in the dielectric layer and comprises first and overlying second MIM capacitors electrically connected in parallel. The first and second MIM capacitors have individual upper and lower electrode plates and different compositions of capacitor dielectric layers.

Metal-insulator-metal capacitor structure having low voltage dependence

Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.

Top via pattern for bond pad structure

An underfilling method for a flip-chip packaging process includes coating a underfill material layer over bumps on a semiconductor substrate, performing a die sawing process on the semiconductor substrate to from a number of dies, and performing a flip-chip process on each of the dies to adhere each of the dies to another substrate. Because the underfill material is coated from the top of the bumps, the air-trapping problem can be eliminated. The process time is shortened to improve yield because the underfill material is dispensed over all the dies before the die-sawing process. This is different from the conventional underfilling process, which has to dispense underfill material and seal edges on each individual die.

Underfilling method for a flip-chip packaging process

A method for burn-in testing a complete wafer comprising the steps of first providing a wafer, and then forming a plurality of bumps thereon. Next, a tape-automated bonding tape having a plurality of bonding pads is designed and fabricated, wherein each bonding pad includes a corresponding circuit and an external contact point. Then, electrical connections between the bonding pads and the bumps are made and a plurality of voltages and currents are supplied through the tape-automated bonding tape for carrying out burn-in tests. Bum-in tests are performed for the whole wafer. Defective chips are singled out after the wafer is cut up and only good chips are used for subsequent packaging. Therefore, production cost can be saved and packaging yield can be increased. Furthermore, a multiple circuit layers design can be employed to fabricate the tape-automated bonding tape. Consequently, circuits necessary for carrying out the burn-in test for the whole wafer is simplified.

Wafer burn-in testing method

Growing community of inventors

Hsinchu, Taiwan

Ming-Hsien Chen