Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Hsiang Song

Jen-Chou Tseng

Tzu-Heng Chang

Jam-Wem Lee

Wun-Jie Lin

Kuo-Ji Chen

Yu-Ti Su

Shu-Chuan Lee

Yu-Der Chih

Shao-Yu Chou

Bo-Ting Chen

Chen-Ming Hung

Tsung-Che Tsai

Yu-Ying Hsu

Harry-Hak-Lay Chuang

Wei-Yu Chen

Bao-Ru Young

Ming Zhu

Kuo-Nan Yang

Yue-Der Chih

Ta-Pen Guo

Shao-Chang Huang

Cheng-Hsiung Kuo

Yi-Feng Chang

Hsiang-Jen Tseng

Po-Nien Chen

Chun-Yu Lin

Han-Jen Yang

Shui-Ming Cheng

Lee-Chung Lu

Ting-Wei Chiang

Chen-Jong Wang

Hung-Cheng Sung

Li-Wei Chu

Chia-Hung Chu

Wen-Chuan Chiang

Sun-Jay Chang

Ker-Min Chen

Chia-Hui Chen

Ming-Hsien Tsai

Huey-Chi Chu

Chang-Fen Hu

Taede Smedes

Johannes Van Zwol

Chewn-Pu Jou

Jian-Hsing Lee

Fu-Lung Hsueh

Kuo-Feng Yu

Hung Cho Wang

Ming Hsien Tsai

Yi-Hsun Wu

Tong-Chern Ong

Wan-Yen Lin

Ting-Wei Chang

Ping-Fang Hung

Chi-Di An

Yu-Hung Chu

Roger Wang

A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.

Device including integrated electrostatic discharge protection component

A device includes first and second standard cells in a layout of an integrated circuit, and first and second active regions. The first standard cell includes an electrostatic discharge (ESD) protection unit, and the second standard cell includes first and second transistors that connect to the ESD protection unit. The first active region includes first, second, and third source/drain regions. The first standard cell includes a first gate arranged across the first active region; and a second gate that is separated from the first gate and is arranged across the first active region and the second active region. The first gate, the first source/drain region and the second source/drain region together correspond to a third transistor of the ESD protection unit. The second gate, the second source/drain region and the third source/drain region together correspond to the first transistor.

A device includes standard cells in a layout of an integrated circuit, the standard cells includes first and second standard cells sharing a first active region and a second active region. The first standard cell includes first and second gates. The first gate includes a first gate finger and a second gate finger that are arranged over the first active region, for forming the first transistor and the second transistor. The second gate is separate from the first gate, the second gate includes a third gate finger and a fourth gate finger that are arranged over the second active region, for forming the third transistor and the fourth transistor. The second standard cell includes a third gate arranged over the first active region and the second active region, for forming the fifth transistor and the sixth transistor. The first to fourth transistors operate as an electrostatic discharge protection circuit.

A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.

Method of forming electrostatic discharge (ESD) testing structure

A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

Memory device with a fuse protection circuit

An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

SCRs with checker board layouts

A device includes an integrated circuit including a single standard cell that is selected from a standard cell library used for design of the layout of the integrated circuit. The single standard cell includes a first active region, a second active region, a first gate, a second gate, and a third gate. The first gate is arranged over the first active region, for formation of at least one first electrostatic discharge (ESD) protection component. The second gate is separate from the first gate, and the second gate is arranged over the second active region, for formation of at least one second ESD protection component. The third gate is separate from the first gate and the second gate, and the third gate is arranged over the first active region and the second active region, for formation of at least one transistor.

A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

An electrostatic discharge (ESD) testing structure includes a measurement device in a first die. The ESD testing structure further includes a fuse in a second die. The ESD testing structure further includes a plurality of bonds electrically connecting the first die to the second die, wherein a first bond of the plurality of bonds electrically connects the fuse to the measurement device.

ESD testing structure, method of using same and method of forming same

A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.

Rotated STI diode on FinFET technology

A method comprises forming an active region including a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by an isolation region, depositing an epitaxial growth block layer over the active region, patterning the epitaxial growth block layer to define a first growth area and a second growth area and growing an N+ region in the first growth area and a P+ region in the second growth area.

Fin ESD protection diode and fabrication method thereof

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Shin-Chu, Taiwan

Ming-Hsiang Song