Boe Technology Group Co., Ltd.

Delta Electronics (shanghai) Co., Ltd

Western Digital Technologies, Inc.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Delta Electronics, Inc.

Sandisk Technologies Inc.

Semiconductor Manufacturing International (shanghai) Corporation

Chongqing Boe Optoelectronics Technology Co., Ltd.

Tencent Technology (shenzhen) Company Limited

Baidu Online Network Technology (beijing) Co., Ltd.

Tufts College

Tusimple, Inc.

Beijing Boe Technology Development Co., Ltd.

Ledvance Gmbh

Boe Technology Groupco., Ltd.

Ming Hsi Wang

Liang Li

Jianping Ying

Ce Zhao

Wei Song

Jie Sun

Jian-Ping Ying

Hong-Jian Gan

Jun Hui Liu

Bin Zhou

Yingbin Hu

Wei Li

Yi Zhang

Tongshang Su

Ming Wang

Dongfang Wang

Feng Qin

Qinghe Wang

Bin Wang

Nan Wang

Hua Xu

Ning Liu

Jun Feng Liu

Jun Wan

Liangchen Yan

Xin Wang

Jing Zhao

Hui Xing Wang

Teng Liu

Lei Zhong

Jie Fu

Cheng Liu

Hui Li

Yanli Zhang

Yang Zhang

Jiahui Yuan

Jun Cheng

Jun Liu

Ling Shi

Xiaobo Huang

Yuankui Ding

Ke Zhang

Zhiming Hu

Chao Yan

Liusong Ni

Bo-Yu Pu

Wei-Liang Fu

Yong Cheng

Qiaobing Xu

Jianlan Luo

Jiaqiang Zhu

Changzhi Xie

Qiancheng Ma

Qi Cao

Yong Shu

Xian Wang

Ben Xu

Bing Zhang

Zhu Liang

Lifeng Qiao

Xiaoping Gu

Ming Ji

Yafei Miao

Xiao Huang

Dongmin Ma

Sishun Zhang

Haitao Wang

Xiaodi Hou

Zheng Wang

Leilei Cheng

Guangyao Li

Shih-Chung Lee

Peng Zhang

Wenchao Bao

Jingang Fang

Moritz Engl

Tao Jiang

Zhao Wang

Xianyong Pu

Xuan Tian

Jianan Hao

Yong Zeng

Guangli Yang

Hailong Wang

Fei Song

Jingjing Xia

Peng Xiao

Li-Feng Qiao

Heekyu Kim

Xiaofei Zhu

Qin Zhen

Chun I Lin

Shaoxiong Wang

Will Li

Dezhao Zhang

Jian-Gang Huang

Yichen Wang

A backlight module includes a rear housing, a light guide plate and a light source. The rear housing includes a bottom wall and a side wall that are connected to each other; the bottom wall and the side wall enclose an accommodation cavity. The light guide plate is located in the accommodation cavity. The light source is located in the accommodation cavity and located between the side wall and a side surface of the light guide plate. The light source includes a circuit board and a plurality of light-emitting devices that are mounted on the circuit board. A surface of the circuit board away from the plurality of light-emitting devices faces the side wall, and light-emitting surfaces of the plurality of light-emitting devices face the side surface of the light guide plate.

Backlight module and display apparatus

The present disclosure provides a method for preparing an interlayer insulating layer and a method for manufacturing a thin film transistor, and a thin film transistor, belongs to the field of display technology, and can solve the problem of poor resistance to breakdown of the interlayer insulating layer in the related art. The method for preparing an interlayer insulating layer includes the following steps: forming a silicon oxide layer with a first reaction gas and forming a silicon nitride layer with a second reaction gas such that hydrogen content in the silicon nitride layer is less than or equal to hydrogen content in the silicon oxide layer.

Method for preparing interlayer insulating layer and method for manufacturing thin film transistor, thin film transistor

The present disclosure provides an array substrate, a method for manufacturing the array substrate, a display panel and a display device. The array substrate includes: a substrate; a planarization layer on a side of the substrate; a pixel defining layer configured to define a pixel opening region and located on a side of the planarization layer away from the substrate; an anode in the pixel opening region and on a side of the planarization layer away from the substrate. The array substrate further includes an intermediate insulation layer between the planarization layer and the pixel defining layer. The intermediate insulation layer has a chemical polarity between a chemical polarity of the planarization layer and a chemical polarity of the pixel defining layer.

Array substrate, manufacture method thereof, display panel and display device

The present disclosure provides a light guide plate, including a light-entering surface, a light-exiting surface adjacent to the light-entering surface, and a bottom surface arranged opposite to the light-exiting surface. The light guide plate includes a central region corresponding to an active display region of a display panel and a peripheral region corresponding a non-display region of the display panel in a first direction, the peripheral region includes a first peripheral region at a side adjacent to the light-entering surface, at least the first peripheral region of the peripheral region has a thickness smaller than the central region in a second direction, the first direction is a direction in which light is propagated inside the light guide plate, and the second direction is a direction in which the light exits the light guide plate. The present disclosure further provides a backlight module and a display device.

Light guide plate, backlight module, and display device

A modular multilevel converter system, and a voltage detection method and an open-circuit fault diagnosis method thereof are disclosed. The modular multilevel converter system includes: N sub-modules sequentially cascaded, where N is an integer greater than or equal to 2, each of the sub-modules comprising at least one bridge arm and a capacitor connected in parallel to the bridge arm, the capacitor having a positive terminal and a negative terminal; and a voltage detection unit for detecting a voltage between at least two adjacent sub-modules in the N sub-modules, the voltage detection unit being connected between the positive terminal of the capacitor of the first sub-module and the negative terminal of the capacitor of the last sub-module in the at least two sub-modules.

Modular multilevel converter system and voltage detection method and open-circuit fault diagnosis method thereof

Technology for open block boundary group programming of non-volatile memory such as NAND. The open block boundary group could potentially be read in response to a request from a host for the data stored in the group. In an aspect, the memory system will determine whether programming a group of memory cells in a selected block will result in an open block. If it will not result in an open block, then the memory system uses a first set of programming parameters to program the group. However, if it will result in an open block then the memory system uses a second set of programming parameters to program the boundary group. The programming parameters may include verify levels and/or a program voltage step size. The second set of programming parameters can tighten Vt distributions, which mitigates mis-reads if the boundary group is read.

Open block boundary group programming for non-volatile memory

The present disclosure provides an image capturing control method and apparatus, an image capturing system and a Time-of-Flight (TOF) camera, capable of solving the problem in the related art that a clear image of an object at a specific distance cannot be captured in harsh weather. The method includes: determining infrared light emission time, exposure start time and exposure end time for a TOF camera based on a predetermined target distance range; transmitting, to the TOF camera, parameter control information containing the infrared light emission time, exposure start time and exposure end time; and receiving an image containing an object located within the target distance range that is captured by the TOF camera in accordance with the parameter control information.

Image capturing control method and apparatus, image capturing system and TOF camera

Memory cells are programmed to threshold voltage distributions that correspond to data states by applying a series of voltage pulses to a selected word line connected to a set of non-volatile memory cells selected for programming. Tighter threshold voltage distributions will result in fewer errors when reading the data at a later time. To create tighter threshold voltage distributions during programming, the system slows down the programming of memory cells as the memory cells approach their target threshold voltage by reducing the effective pulse width of the voltage pulses. The voltage pulses are divided into portions, with each portion corresponding to a subset of the pulse width or a subset of the time period that the voltage pulse is applied. Memory cells that are approaching their target threshold voltage will be slowed down by inhibiting those memory cells from programming during later-in-time portions of the voltage pulses.

Non-volatile memory with precise programming

To remedy short term data retention issues, a non-volatile memory performs a multi-pass programming process to program data into a set of non-volatile memory cells and identifies non-volatile memory cells that experienced downward threshold voltage drift after a first pass of the multi-pass programming process and prior to a final pass of the multi-pass programming process. The final pass of the multi-pass programming process comprises programming non-volatile memory cells not identified to have experienced the downward threshold voltage drift to a set of final target threshold voltages and purposefully overprogramming non-volatile memory cells identified to have experienced the downward threshold voltage drift to threshold voltages greater than respective final target threshold voltages by one or more offsets.

Non-volatile memory with intentional overprogramming to improve short term data retention issue

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages associated with the data states targeted for each of the memory cells being programmed during verify loops of a program-verify operation. The control means slows the memory cells targeted for a selected one of the data states identified as being faster to program than other ones of the memory cells during one of verify loops associated with an earlier one of data states.

State look ahead quick pass write algorithm to tighten ongoing natural threshold voltage of upcoming states for program time reduction

To increase the speed of programming of a multi-plane non-volatile memory, it is proposed to accelerate the programming of the last one or more data states for one or more slow planes.

Non-volatile memory with enhanced program operation for last state on slow plane

The present disclosure relates to vehicle technology, and more particularly, to a vehicle for carrying a container. The vehicle includes: a vehicle body, at least one locking mechanism provided on the vehicle body and a microcontroller unit communicatively connected to each of the at least one locking mechanism and configured to control each of the at least one locking mechanism to switch between a locked state and an unlocked state. Each of the at least one locking mechanism is connected fixedly to the container when the locking mechanism is in the locked state, such that the container is fixed to the vehicle body. The vehicle is advantageous in that it is capable of locking and unlocking the container in a simple way, thereby improving the efficiency of the vehicle in transportation of the container.

Vehicle for carrying containers

An apparatus is provided that includes a memory die having a first memory cell, and a controller connected to the memory die. The controller is configured to apply a plurality of programming pulses to the first memory cell, apply a plurality of first verify pulses to the first memory cell, determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state, apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state, determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state, and apply an additional programming pulse to the first memory cell.

Apparatus and methods for programming memory cells

Provided are a display unit and a display apparatus, the display unit includes a back plate and a print circuit board disposed on the back plate, wherein the print circuit board is connected to the back plate through a screw, and is provided with a first electrostatic discharge region and a first electrostatic discharge unit; the first electrostatic discharge region is connected to the back plate through the screw to form a first electrostatic discharge channel, and the first electrostatic discharge unit is connected to the back plate to form a second electrostatic discharge channel.

Display unit and display apparatus

The present invention relates to an antibody binding to lymphocyte activation gene-3 (LAG-3) and use thereof.

Lymphocyte activation gene-3 (LAG-3) binding antibody and use thereof

Growing community of inventors

Beijing, China

Ming Hsi Wang