Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Ho Tsai

Jyun-Hong Chen

Chi-Ming Tsai

Yung-Hsiang Chen

Wen-Hao Cheng

Dong-Hsu Cheng

Peng-Ren Chen

Yu-Nu Hsu

Chih-Chung Huang

Chun-Chen Liu

Chih-Chiang Tu

Ching-Hung Lai

Chung-Hung Lin

Chun-Jen Chen

Che-Yuan Chang

Jun-Hua Chen

Jim Liang

A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

Semiconductor device

A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.

Semiconductor device manufacturing method and associated semiconductor die

A photomask includes a transparent substrate and a shielding pattern disposed on the transparent substrate. The shielding pattern includes shielding island structures. The shielding island structures are separated from and spaced apart from one another by dividing lanes. The dividing lanes expose the underlying transparent substrate. The photomask is configured for a light of a wavelength, and the dividing lanes reduce or hinder a transmission of the light of the wavelength.

Photomask, photolithography system and manufacturing process

A mask includes a transparent substrate, a first pattern, a second pattern, and a sub-resolution auxiliary feature. The first pattern and the second pattern are over the transparent substrate. The first pattern has an area of 0.16 &#x3bc;mto 60000 &#x3bc;m. The second pattern has an area of 0.16 &#x3bc;mto 60000 &#x3bc;m. The sub-resolution auxiliary feature is over the transparent substrate and connects the first pattern and the second pattern.

Mask and photolithography system

The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron&#xd7;10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.

Structure and method for E-beam in-chip overlay mark

A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.

System and method for lithography exposure with correction of overlay shift induced by mask heating

Growing community of inventors

Hsinchu, Taiwan

Ming-Ho Tsai