Samsung Electronics Co., Ltd.

Ming He

Harsono S Simka

Rebecca Park

Mehdi Saremi

Daewon Ha

Byounghak Hong

Kang-ill Seo

Inchan Hwang

Sang Hoon Ahn

Seungchan Yun

Jeonghyuk Yim

Gunho Jo

Anthony Dongick Lee

JaeHyun Park

Chihak Ahn

Seowoo Nam

Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

Nanosheet transistor devices and related fabrication methods

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods

Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.

Integrated circuit devices including a via and methods of forming the same

A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.

Fully aligned via integration with selective catalyzed vapor phase grown materials

Growing community of inventors

San Jose, CA, United States of America

Ming He