Marvellworld Trade Ltd.

Marvell International Limited

Invensense, Inc.

Ming He

David M Signoff

Wayne A Loeb

Renaldi Winoto

Li Lin

Shu-Hsien Liao

Philip Godoy

Sai-Wang Tam

Jinho Park

Yuan Lu

Richelle L Smith

Nuntha Kumar Krishnasamy Maniam

Jialin Liu

Xinhua Chen

Implementation of large temperature-insensitive resistance in CMOS using short-duty-clock cycle is provided herein. Operations of a method can comprise boosting a resistance level of a switched-resistor circuit to a defined resistance level. The boosting can comprise using a short-duty-cycle clock to facilitate the boosting. Also provided is a sensor system that can comprise a short-duty-cycle clock and a switched-resistor circuit. The short-duty cycle clock boosts a resistance level of the switched-resistor circuit to a defined resistance level.

Implementing process, voltage, and/or temperature-insensitive resistance in complementary metal-oxide-semiconductors using a short-duty-clock cycle

A circuit includes a reference voltage circuit, a filter circuit configured to receive an output of the reference voltage circuit, and a voltage follower configured to receive an output of the filter circuit and generate a bias voltage. The filter circuit is configured to combine signals on a reference ground with the output of the reference voltage circuit. A method of providing a bias voltage includes generating a reference voltage using a reference voltage circuit, filtering the reference voltage to generate a second voltage using a filter circuit, and generating the bias voltage according to the second voltage using a voltage follower circuit. Filtering the reference voltage includes combining a fluctuation of the reference ground with the reference voltage.

Memory effect reduction using low impedance cascode biasing

A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.

Memory effect reduction using low impedance biasing

A radio-frequency amplifier includes a matching network comprising a switching unit. The switching unit is operable in a first condition to provide a selected impedance at a first selected frequency. The switching unit is operable in a second condition to form a bandstop filter. A stop band of the bandstop filter includes a second selected frequency. The first selected frequency may be a second harmonic of a transmission frequency different from the second selected frequency. A multi-band transceiver is also described, as is a method of transmitting a first signal and a second signal.

Selectable-input-impedance radio-frequency reception amplifier

A transformer includes a first loops and second loops. The first loops include a first set of input terminals. The first loops include at least three loops that are conductively coupled to each other in series by first crossovers. The second loops include a first set of output terminals. The second loops include at least three loops that are conductively coupled to each other in series by second crossovers. Each of the second conductive loops is inductively coupled to and nested within a respective one of the first conductive loops.

Transformer circuits having transformers with figure eight and double figure eight nested structures

Systems and methods for power amplification using multiple digital amplifiers are provided. A power amplifier includes a first digital amplifier configured to process a digital input signal to generate a first analog output signal. The first analog output signal is configured to have a magnitude corresponding to amplitude information of the digital input signal. The power amplifier further includes a second digital amplifier configured to process an adjusted digital input signal to generate a second analog output signal. The second analog output signal is configured to have a magnitude corresponding to amplitude information of the adjusted digital input signal. An adjustment module configured to adjust amplitude information and phase information of the digital input signal generates the adjusted digital input signal. The digital input signal is adjusted to control a relationship between the first analog output signal and the second analog output signal.

Digital power amplifier

In accordance with an embodiment of the disclosure, systems and methods are provided for multi-modal power amplification. In certain implementations, an adjustable power amplifier amplifies an input signal, and the amount of amplification is varied based on the input signal. A variable impedance unit receives an amplified input signal, and the amount of load impedance at the variable impedance unit is varied based on the input signal.

Systems and methods for performing multi-modal power amplification

Disclosed is a transmit/receive circuit arrangement wherein a transceiver circuit including a transmit/receive switch is fabricated on an integrated circuit chip. A matching network is wholly disposed off-chip relative to the integrated circuit chip. In embodiments, at least a portion of the matching network is formed off-chip and a portion of the matching network is formed on-chip.

RF front-end with integrated T/R switch

A system including a power amplifier having a first gain, a preamplifier having a second gain, a first temperature sensor configured to sense the temperature of the power amplifier, and a bias generator. The first gain is a function of a temperature of the power amplifier. The preamplifier receives an input signal, amplifies the input signal according to the second gain, and outputs an amplified signal to the power amplifier. The bias generator generates a biasing signal to bias the preamplifier and adjusts the second gain of the preamplifier by adjusting the biasing signal based on the temperature of the power amplifier and an ambient temperature. The adjusted second gain of the preamplifier compensates a change in the first gain of the power amplifier due to a change in the temperature of the power amplifier.

Cancellation of gain change due to amplifier self-heating

A system includes a power amplifier, a preamplifier, a first temperature sensor, and a bias generator. The power amplifier has a first gain, which is a function of a temperature of the power amplifier. The preamplifier has a second gain, amplifies an input signal, and outputs an amplified signal to the power amplifier. The first temperature sensor senses the temperature and generates a first signal. The bias generator generates a first biasing signal to bias the power amplifier, generates a second biasing signal to bias the preamplifier, and adjusts the second gain by adjusting the second biasing signal based on the first signal. The adjusted second gain compensates a change in the first gain due to the change in the temperature.

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Fremont, CA, United States of America

Ming He