Globalfoundries Inc.

Arm Limited

International Business Machines Corporation

Cisco Technology, Inc.

Stmicroelectronics Gmbh

Cerfe Labs, Inc.

Ming He

Xunyuan Zhang

Sean Xuan Lin

Larry Zhao

Errol Todd Ryan

Paul Raymond Besser

Kunaljeet Tanwar

John A Iacoponi

Craig Child

Seowoo Nam

Nicholas V Licausi

Christian Witt

Jingyan Zhang

Moosung M Chae

Keith Donegan

Ailian Zhao

Manuj Rathor

Anbu Selvam Km Mahalingam

Colin Bombardier

Theodorus E Standaert

Yann Mignot

Hyun-Jin Cho

Roderick Alan Augur

Jolanta Bozena Celinska

Somnath Ghosh

Vikrant Kumar Chauhan

Prakash Periasamy

Jim E Kelly

Eswar Ramanathan

Ashwini Chandrashekar

Qanit Takmeel

Jeric Sarad

Raghuveer Patlotta

Eric Lerner

Isaac Eleftheriadis

Ruixiang Ray Liu

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, an insulative material may be formed on or over a sidewall portion of a conductive contact region. The insulative material may insulate the conductive contact region from resputtered CEM occurring during a physical etch of a CEM film.

Correlated electron material (CEM) devices with contact region sidewall insulation

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch may include removing of an exposed portion of a CEM film to form an exposed sidewall region bordering a remaining unexposed portion of the CEM film under or beneath a conductive overlay. The method may further include at least partially restoring properties of the exposed sidewall region to a CEM via exposure of the exposed sidewall region to one or more gaseous annealing agents.

Formation of correlated electron material (CEM) devices with restored sidewall regions

Disclosed is a method for the fabrication of a correlated electron material (CEM) switching device, the method comprising: forming a layer of a conductive substrate; forming a layer of a correlated electron material on the conductive substrate; forming a layer of a conductive overlay on the layer of correlated electron material; and patterning the layers whereby to form a stack comprising a conductive substrate, a CEM layer and a conductive overlay, wherein the patterning comprises the following steps: forming a hard mask on the layer of the conductive overlay; dry etching the layer of conductive overlay and the layer of correlated electron material whereby to form a partially formed stack; depositing a coating of a protective polymer over at least sidewalls of the partially formed stack; and dry etching the layer of conductive substrate.

Method for fabrication of a CEM device

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments a method may include forming a structure on a first portion of a substrate while maintaining a second portion of the substrate exposed. A sealing layer may be deposited over the structure and over at least a portion of the exposed second portion of the substrate. A conductive via may be formed by way of a dry etch through the sealing layer to contact the exposed metal layer. In embodiments, an etch-stop control layer may be utilized to control an etching process prior to formation of metal contacts over the CEM switch and the conductive via.

Fabrication of correlated electron material (CEM) devices

Disclosed is a method for the fabrication of a correlated electron material (CEM) device comprising: forming a layer of a conductive substrate on a substrate; forming a layer of a correlated electron material on the layer of conductive substrate; forming a layer of a conductive overlay on the layer of correlated electron material; patterning these layers to form a stack comprising a conductive substrate, a CEM layer and a conductive overlay, on the substrate; forming a cover layer of an insulating material over the stack; and patterning the cover layer wherein: the patterning of the cover layer comprises etching a trench in the cover layer whereby to expose the conductive overlay; and the method further comprises treating the exposed conductive overlay to remove an oxidation layer there from.

Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

Substrate structure with spatial arrangement configured for coupling of surface plasmons to incident light

An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

Semiconductor device having a self-forming barrier layer at via bottom

Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.

Multi-directional self-aligned multiple patterning

Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.

Integrated circuits including magnetic tunnel junctions for magnetoresistive random-access memory and methods for fabricating the same

Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect in a first interlayer dielectric. A first cap is formed overlying the first interlayer dielectric adjacent to the interconnect, and a second interlayer dielectric is formed overlying the first interlayer dielectric, the interconnect, and the cap. A contact is formed through the second interlayer dielectric, where the contact includes an overlap region and a connection region. The overlap region directly overlies the first interlayer dielectric adjacent to the interconnect, and the connection region directly contacts the interconnect. The first cap is positioned between the overlap region and the first interlayer dielectric.

Integrated circuits with self aligned contacts and methods of manufacturing the same

Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.

Methods of producing integrated circuits with an air gap

One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Copper based nitride liner passivation layers for conductive copper structures

A method of forming a thinner barrier/liner stack for vias and metal lines and the resulting device are disclosed. Embodiments include forming a via through an interlayer dielectric (ILD) and capping layer, down to a first metal layer; forming a moisture scavenging layer precursor over the ILD and on side and bottom surfaces of the via; annealing the moisture scavenging layer precursor, forming a moisture scavenging layer; forming a barrier/liner stack over the moisture scavenging layer; and depositing a second metal layer over the barrier/liner stack and filling the via and trench.

Moisture scavenging layer for thinner barrier application in beol integration

A user associated with a first organization is authenticated, via a meeting server, for participation in an online session hosted by a second organization. It is determined, via the meeting server, that the first organization requires the user to accept a first policy. It is also determined, via the meeting server, that the second organization requires the user to accept a second policy. The first policy and the second policy are presented to the user for acceptance.

Acceptance of policies for cross-company online sessions

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask.

Growing community of inventors

Slingerlands, NY, United States of America

Ming He