Industrial Technology Research Institute

Ming-Fen Lin

Ming-Tsan Kao

Ming-Mao Chiang

Ruen-rone Lee

Chieh-Chih Chang

Won-Yih Lin

Chin-Chen Chang

Chien-Lin Lien

Tung-Chieh Tsai

Ding-Zhou Duan

Chung-Ching Chen

Shu-Kai Yang

Hsiang-Chi Lin

A method of operating a fuzzy inference system to simplify a mesh capable of producing a high-quality approximate mesh and retaining good characteristics and appearance so that a good visual effect emerges. The invention utilizes a fuzzy inference system to integrate mesh attributes and estimate the cost in removing certain data, which serve as a criteria for mesh simplification. Hence, the invention is suitable for progressive meshes, multiresolution modeling rendering and progressive transmission on a network.

Fuzzy inference system for simplifying mesh

A method of area partition in virtual environment is disclosed. It can be used to divide 3D (Three Dimensions) virtual environment into several subareas. The invention interposes neighboring subareas so that the subareas in the same plane and the subareas in adjacent planes mix with one another. Both the number of subareas adjacent to each subarea and the number of subareas an object crosses can be decreased, thus lowering the load in operations.

Method of area partition in virtual environment

Texture mapping of a primitive object uses multiple levels of detail. The primitive object is a triangle having three vertices. The pixel coordinates of the three vertices and their corresponding texture mapped coordinates satisfy three linear equations derived from the equation representing the plane on which the triangle belongs to. An equivalent formula derived from a standard formula for the multiple levels of detail can be computed by a plurality of constants forming the three linear equations. The plurality of constants are first determined by using the pixel coordinates and the corresponding texture mapped coordinates of the three vertices. By substituting the constants into the equivalent formula, the value for the multiple levels of detail can be computed. A lookup table is used to determine log function values that are required in the equivalent formula. The method can be realized by simple hardware and a high precision log lookup table to accomplish high quality texture mapping.

Apparatus and method for texture mapping using multiple levels of detail

A cache device and a method of using the same for data accesses according to the invention. Particularly, the cache device has a prefetch queue comparing circuit which comprises a cache hit/miss judging circuit, an address queue register and a prefetch condition judging circuit. The cache hit/miss judging circuit is used to judge whether a currently-read address coming from a bus is of cache hit or cache miss, wherein the address consists of an index address and a tag address. The address queue register directly stores the index address of the currently-read address plus a corresponding first one-bit flag signal if the cache hit/miss judging circuit judges that the currently-read address is of cache hit. The prefetch condition judging circuit is used to judge whether the index address of the currently-read address is the same as any index addresses already stored in the address queue register if the cache hit/miss judging circuit judges that the currently-read address is of cache miss. If the index address is not the same as any index address still stored in the address queue register, a corresponding tag address and data originally stored in a tag memory and a data memory, respectively are renewed in an asynchronous way.

Cache memory device with prefetch function and method for asynchronously renewing tag addresses and data during cache miss states

An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f,<f,<f,or 0.5f,<f,<f,, where f,is the write frequency if f,is the read frequency, or vice versa. A FIFO in accordance with the present invention comprises a dual port random access memory, a read pointer, a write pointer, a synchronization circuit and a status indicator. In the FIFO design, the read pointer indicating the read address is a simple sequential counter, and the write pointer indicating the write address is a Gray code counter. Gray code to sequential count converters are used to convert the Gray codes to sequential counts. The synchronization circuit synchronizes the write pointer and the read pointer using a read clock. A status indicator with simple circuits is provided to indicate if the FIFO is almost full or empty.

Apparatus and method for asynchronous dual port FIFO

Disclosed is an improved computer graphics memory architecture. The architecture includes an address translation table (ATT) and a buffer. The address translation table receives information about desired pixel data and determines the physical address of the desired data. The buffer is connected to the ATT and has a dual bank which stores the color value and the Z value of a 3-D pixel. A buffer addressing method is also provided in which the address of the desired pixel information and associated control circuits may be quickly determined through an appropriate data arrangement in the buffer and an address transfer table.

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Hsinchu, Taiwan

Ming-Fen Lin